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[Qemu-arm] [PATCH v3-a 15/27] target/arm: Implement SVE Integer Arithmet
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v3-a 15/27] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group |
Date: |
Wed, 16 May 2018 15:29:55 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-sve.c | 34 ++++++++++++++++++++++++++++++++++
target/arm/sve.decode | 13 +++++++++++++
2 files changed, 47 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index f14bb2196a..d9c4118d46 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -251,6 +251,40 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a,
uint32_t insn)
return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
}
+/*
+ *** SVE Integer Arithmetic - Unpredicated Group
+ */
+
+static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm);
+}
+
/*
*** SVE Integer Arithmetic - Binary Predicated Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 5e4335b2ae..58d59c7b77 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -66,6 +66,9 @@
# Three predicate operand, with governing predicate, flag setting
@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
+# Three operand, vector element size
address@hidden ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
+
# Two register operand, with governing predicate, vector element size
@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
&rprr_esz rn=%reg_movprfx
@@ -203,6 +206,16 @@ MLS 00000100 .. 0 ..... 011 ... ..... .....
@rda_pg_rn_rm
MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
+### SVE Integer Arithmetic - Unpredicated Group
+
+# SVE integer add/subtract vectors (unpredicated)
+ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
+SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
+SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
+UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
+SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
+UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
+
### SVE Logical - Unpredicated Group
# SVE bitwise logical operations (unpredicated)
--
2.17.0
- [Qemu-arm] [PATCH v3-a 05/27] target/arm: Implement SVE predicate test, (continued)
- [Qemu-arm] [PATCH v3-a 05/27] target/arm: Implement SVE predicate test, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 06/27] target/arm: Implement SVE Predicate Logical Operations Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 07/27] target/arm: Implement SVE Predicate Misc Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 09/27] target/arm: Implement SVE Integer Reduction Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 08/27] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 12/27] target/arm: Implement SVE bitwise shift by wide elements (predicated), Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 11/27] target/arm: Implement SVE bitwise shift by vector (predicated), Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 10/27] target/arm: Implement SVE bitwise shift by immediate (predicated), Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 15/27] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group,
Richard Henderson <=
- [Qemu-arm] [PATCH v3-a 14/27] target/arm: Implement SVE Integer Multiply-Add Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 16/27] target/arm: Implement SVE Index Generation Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 13/27] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 17/27] target/arm: Implement SVE Stack Allocation Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 19/27] target/arm: Implement SVE Compute Vector Address Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 18/27] target/arm: Implement SVE Bitwise Shift - Unpredicated Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 21/27] target/arm: Implement SVE floating-point trig select coefficient, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 20/27] target/arm: Implement SVE floating-point exponential accelerator, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 23/27] target/arm: Implement SVE Bitwise Immediate Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 22/27] target/arm: Implement SVE Element Count Group, Richard Henderson, 2018/05/16