Re: [Qemu-arm] [PATCH v3 21/31] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16

[Richard Henderson]

On 02/23/2018 07:36 AM, Alex Bennée wrote:
> Neither of these operations alter the floating point status registers
> so we can do a pure bitwise operation, either squashing any sign
> bit (ABS) or inverting it (NEG).
> 
> Signed-off-by: Alex Bennée <address@hidden>
> 
> ---
> v3
>   - fixup re-base conflicts
>   - make both operations pure bitwise TCG
> ---
>  target/arm/translate-a64.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <address@hidden>


r~