Re: [Qemu-arm] [PATCH v2 0/7] target/arm: More SVE prep work

[Peter Maydell]

On 11 February 2018 at 20:58, Richard Henderson
<address@hidden> wrote:
> Changes for v2:
> Include signal frames and PR_SVE_SET/GET_VL.
>
>
> Blurb for v1:
> First, we had noted that ARM_CP_64BIT needed to be removed from
> the ZCR_EL registers, but the patch set was applied without
> actually fixing that.
>
> Second, there's an existing bug by which the FPCR/FPSR registers
> are not properly trapped when FP is disabled.  Fix that with a
> translation-time check.
>
> Third, my attempt at using .accessfn for ZCR_EL fails to take
> into account the two different exception syndromes that must be
> raised.  Although they probably aren't as important as FPCR/FPSR,
> handle them at translation time too.
>
> Fourth, when writing to an AdvSIMD register, zero the rest of
> the SVE register.
>
>
> r~
>
>
> Richard Henderson (7):
>   target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
>   target/arm: Enforce FP access to FPCR/FPSR
>   target/arm: Suppress TB end for FPCR/FPSR
>   target/arm: Enforce access to ZCR_EL at translation
>   target/arm: Handle SVE registers when using clear_vec_high
>   linux-user: Support SVE in aarch64 signal frames
>   linux-user: Implement aarch64 PR_SVE_SET/GET_VL

Hi; I've applied patches 1..5 to target-arm.next, and left
review comments for 6 and 7.

thanks
-- PMM