[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH v5 8/9] xlnx-zynqmp-pmu: Connect the IPI device to the
From: |
Alistair Francis |
Subject: |
[Qemu-arm] [PATCH v5 8/9] xlnx-zynqmp-pmu: Connect the IPI device to the PMU |
Date: |
Tue, 16 Jan 2018 15:22:39 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
V4:
- Move the IPI to the machine instead of the SoC
hw/microblaze/xlnx-zynqmp-pmu.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
index 828eeedc9f..14b8ed4a43 100644
--- a/hw/microblaze/xlnx-zynqmp-pmu.c
+++ b/hw/microblaze/xlnx-zynqmp-pmu.c
@@ -24,6 +24,7 @@
#include "cpu.h"
#include "boot.h"
+#include "hw/intc/xlnx-zynqmp-ipi.h"
#include "hw/intc/xlnx-pmu-iomod-intc.h"
/* Define the PMU device */
@@ -38,6 +39,15 @@
#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
+#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
+
+static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
+ 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
+};
+static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
+ 19, 20, 21, 22,
+};
+
typedef struct XlnxZynqMPPMUSoCState {
/*< private >*/
DeviceState parent_obj;
@@ -136,6 +146,9 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
+ XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
+ qemu_irq irq[32];
+ int i;
/* Create the ROM */
memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
@@ -155,6 +168,24 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
&error_abort);
object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
+ for (i = 0; i < 32; i++) {
+ irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);
+ }
+
+ /* Create and connect the IPI device */
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
+ ipi[i] = g_new0(XlnxZynqMPIPI, 1);
+ object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
+ qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default());
+ }
+
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
+ object_property_set_bool(OBJECT(ipi[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
+ }
+
/* Load the kernel */
microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
machine->ram_size,
--
2.14.1
This email and any attachments are intended for the sole use of the named
recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
recipient, do not read, copy, or forward this email message or any attachments.
Delete this email message and any attachments immediately.
- [Qemu-arm] [PATCH v5 2/9] xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU, (continued)
- [Qemu-arm] [PATCH v5 2/9] xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 1/9] microblaze: boot.c: Don't try to find NULL pointer, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 3/9] xlnx-zynqmp-pmu: Add the CPU and memory, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 4/9] aarch64-softmmu.mak: Use an ARM specific config, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 6/9] xlnx-zynqmp-pmu: Connect the PMU interrupt controller, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 5/9] xlnx-pmu-iomod-intc: Add the PMU Interrupt controller, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 7/9] xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 8/9] xlnx-zynqmp-pmu: Connect the IPI device to the PMU,
Alistair Francis <=
- Re: [Qemu-arm] [PATCH v5 0/9] Add the ZynqMP PMU and IPI, Alistair Francis, 2018/01/16