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Re: [Qemu-arm] [PATCH 0/2] GICv2 & GICv3: RAZ/WI reserved addresses rath
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From: |
Ard Biesheuvel |
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Subject: |
Re: [Qemu-arm] [PATCH 0/2] GICv2 & GICv3: RAZ/WI reserved addresses rather than aborting |
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Date: |
Thu, 14 Dec 2017 13:59:30 +0100 |
On 13 December 2017 at 16:54, Peter Maydell <address@hidden> wrote:
> On 13 December 2017 at 16:52, Peter Maydell <address@hidden> wrote:
>> The GICv2 and GICv3 specifications say that reserved register
>> addresses should RAZ/WI. This means we need to return MEMTX_OK, not
>> MEMTX_ERROR, because now that we support generating external aborts
>> the latter will cause an abort on new board models.
>>
>> In particular, at least some versions of UEFI try to
>> access a reserved address in the GICv3 redistributor
>> (at SGI_base + 0x184) and fail to boot on the virt board
>> without this.
>>
Could this commit
https://github.com/tianocore/edk2/commit/28f8d28faabf50a82ef8d137308592c64ea9e2b6
have anything to do with that?