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[Qemu-arm] [PATCH 0/2] GICv2 & GICv3: RAZ/WI reserved addresses rather t
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 0/2] GICv2 & GICv3: RAZ/WI reserved addresses rather than aborting |
Date: |
Wed, 13 Dec 2017 16:52:19 +0000 |
The GICv2 and GICv3 specifications say that reserved register
addresses should RAZ/WI. This means we need to return MEMTX_OK, not
MEMTX_ERROR, because now that we support generating external aborts
the latter will cause an abort on new board models.
In particular, at least some versions of UEFI try to
access a reserved address in the GICv3 redistributor
(at SGI_base + 0x184) and fail to boot on the virt board
without this.
thanks
-- PMM
Peter Maydell (2):
hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI
hw/intc/arm_gic: reserved register addresses are RAZ/WI
hw/intc/arm_gic.c | 5 +++--
hw/intc/arm_gicv3_dist.c | 13 +++++++++++++
hw/intc/arm_gicv3_its_common.c | 8 +++-----
hw/intc/arm_gicv3_redist.c | 13 +++++++++++++
4 files changed, 32 insertions(+), 7 deletions(-)
--
2.7.4
- [Qemu-arm] [PATCH 0/2] GICv2 & GICv3: RAZ/WI reserved addresses rather than aborting,
Peter Maydell <=