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[Qemu-arm] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL re
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL register on exception return |
Date: |
Fri, 22 Sep 2017 15:59:52 +0100 |
On exception return for v8M, the SPSEL bit in the EXC_RETURN magic
value should be restored to the SPSEL bit in the CONTROL register
banked specified by the EXC_RETURN.ES bit.
Add write_v7m_control_spsel_for_secstate() which behaves like
write_v7m_control_spsel() but allows the caller to specify which
CONTROL bank to use, reimplement write_v7m_control_spsel() in
terms of it, and use it in exception return.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 40 +++++++++++++++++++++++++++-------------
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a3c63c3..4444d04 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6052,28 +6052,42 @@ static bool v7m_using_psp(CPUARMState *env)
env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;
}
-/* Write to v7M CONTROL.SPSEL bit. This may change the current
- * stack pointer between Main and Process stack pointers.
+/* Write to v7M CONTROL.SPSEL bit for the specified security bank.
+ * This may change the current stack pointer between Main and Process
+ * stack pointers if it is done for the CONTROL register for the current
+ * security state.
*/
-static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
+static void write_v7m_control_spsel_for_secstate(CPUARMState *env,
+ bool new_spsel,
+ bool secstate)
{
- uint32_t tmp;
- bool new_is_psp, old_is_psp = v7m_using_psp(env);
+ bool old_is_psp = v7m_using_psp(env);
- env->v7m.control[env->v7m.secure] =
- deposit32(env->v7m.control[env->v7m.secure],
+ env->v7m.control[secstate] =
+ deposit32(env->v7m.control[secstate],
R_V7M_CONTROL_SPSEL_SHIFT,
R_V7M_CONTROL_SPSEL_LENGTH, new_spsel);
- new_is_psp = v7m_using_psp(env);
+ if (secstate == env->v7m.secure) {
+ bool new_is_psp = v7m_using_psp(env);
+ uint32_t tmp;
- if (old_is_psp != new_is_psp) {
- tmp = env->v7m.other_sp;
- env->v7m.other_sp = env->regs[13];
- env->regs[13] = tmp;
+ if (old_is_psp != new_is_psp) {
+ tmp = env->v7m.other_sp;
+ env->v7m.other_sp = env->regs[13];
+ env->regs[13] = tmp;
+ }
}
}
+/* Write to v7M CONTROL.SPSEL bit. This may change the current
+ * stack pointer between Main and Process stack pointers.
+ */
+static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
+{
+ write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure);
+}
+
void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
{
/* Write a new value to v7m.exception, thus transitioning into or out
@@ -6369,7 +6383,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
* Handler mode (and will be until we write the new XPSR.Interrupt
* field) this does not switch around the current stack pointer.
*/
- write_v7m_control_spsel(env, return_to_sp_process);
+ write_v7m_control_spsel_for_secstate(env, return_to_sp_process,
exc_secure);
switch_v7m_security_state(env, return_to_secure);
--
2.7.4
- [Qemu-arm] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset, (continued)
- [Qemu-arm] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 04/20] target/arm: Restore security state on exception return, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 03/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 08/20] target/arm: Don't warn about exception return with PC low bit set for v8M, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 07/20] target/arm: Warn about restoring to unaligned stack, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL register on exception return,
Peter Maydell <=
- [Qemu-arm] [PATCH 10/20] target/arm: Update excret sanity checks for v8M, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 09/20] target/arm: Add new-in-v8M SFSR and SFAR, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 11/20] target/arm: Add support for restoring v8M additional state context, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 12/20] target/arm: Add v8M support to exception entry code, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 17/20] target/arm: Implement SG instruction, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 02/20] target/arm: Don't switch to target stack early in v7M exception return, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 15/20] target/arm: Fix calculation of secure mm_idx values, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 13/20] nvic: Implement Security Attribution Unit registers, Peter Maydell, 2017/09/22