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[Qemu-arm] [PATCH 15/19] nvic: Handle v8M changes in nvic_exec_prio()
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 15/19] nvic: Handle v8M changes in nvic_exec_prio() |
Date: |
Tue, 12 Sep 2017 19:14:02 +0100 |
Update nvic_exec_prio() to support the v8M changes:
* BASEPRI, FAULTMASK and PRIMASK are all banked
* AIRCR.PRIS can affect NS priorities
* AIRCR.BFHFNMINS affects FAULTMASK behaviour
These changes mean that it's no longer possible to
definitely say that if FAULTMASK is set it overrides
PRIMASK, and if PRIMASK is set it overrides BASEPRI
(since if PRIMASK_NS is set and AIRCR.PRIS is set then
whether that 0x80 priority should take effect or the
priority in BASEPRI_S depends on the value of BASEPRI_S,
for instance). So we switch to the same approach used
by the pseudocode of working through BASEPRI, PRIMASK
and FAULTMASK and overriding the previous values if
needed.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/armv7m_nvic.c | 51 ++++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 42 insertions(+), 9 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 91d2f33..b13327d 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -319,18 +319,51 @@ static void nvic_recompute_state(NVICState *s)
static inline int nvic_exec_prio(NVICState *s)
{
CPUARMState *env = &s->cpu->env;
- int running;
+ int running = NVIC_NOEXC_PRIO;
- if (env->v7m.faultmask[env->v7m.secure]) {
- running = -1;
- } else if (env->v7m.primask[env->v7m.secure]) {
+ if (env->v7m.basepri[M_REG_NS] > 0) {
+ running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
+ }
+
+ if (env->v7m.basepri[M_REG_S] > 0) {
+ int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
+ if (running > basepri) {
+ running = basepri;
+ }
+ }
+
+ if (env->v7m.primask[M_REG_NS]) {
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
+ if (running > NVIC_NS_PRIO_LIMIT) {
+ running = NVIC_NS_PRIO_LIMIT;
+ }
+ } else {
+ running = 0;
+ }
+ }
+
+ if (env->v7m.primask[M_REG_S]) {
running = 0;
- } else if (env->v7m.basepri[env->v7m.secure] > 0) {
- running = env->v7m.basepri[env->v7m.secure] &
- nvic_gprio_mask(s, env->v7m.secure);
- } else {
- running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
}
+
+ if (env->v7m.faultmask[M_REG_NS]) {
+ if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
+ running = -1;
+ } else {
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
+ if (running > NVIC_NS_PRIO_LIMIT) {
+ running = NVIC_NS_PRIO_LIMIT;
+ }
+ } else {
+ running = 0;
+ }
+ }
+ }
+
+ if (env->v7m.faultmask[M_REG_S]) {
+ running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
+ }
+
/* consider priority of active handler */
return MIN(running, s->exception_prio);
}
--
2.7.4
- [Qemu-arm] [PATCH 07/19] nvic: Implement NVIC_ITNS<n> registers, (continued)
- [Qemu-arm] [PATCH 07/19] nvic: Implement NVIC_ITNS<n> registers, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 12/19] nvic: In escalation to HardFault, support HF not being priority -1, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 10/19] nvic: Make SHPR registers banked, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 09/19] nvic: Make set_pending and clear_pending take a secure parameter, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 01/19] target/arm: Implement MSR/MRS access to NS banked registers, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 15/19] nvic: Handle v8M changes in nvic_exec_prio(),
Peter Maydell <=
- [Qemu-arm] [PATCH 13/19] nvic: Implement v8M changes to fixed priority exceptions, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 18/19] nvic: Make SHCSR banked for v8M, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 11/19] nvic: Compare group priority for escalation to HF, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 08/19] nvic: Handle banked exceptions in nvic_recompute_state(), Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 14/19] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear, Peter Maydell, 2017/09/12