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[Qemu-arm] [RFC PATCH for 2.11 17/23] fpu/softfloat2a: implement propaga
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [RFC PATCH for 2.11 17/23] fpu/softfloat2a: implement propagateFloat16NaN |
Date: |
Thu, 20 Jul 2017 16:04:20 +0100 |
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.
Signed-off-by: Alex Bennée <address@hidden>
---
fpu/softfloat2a/softfloat-specialize.h | 43 ++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/fpu/softfloat2a/softfloat-specialize.h
b/fpu/softfloat2a/softfloat-specialize.h
index de2c5d5702..c8282b8bf7 100644
--- a/fpu/softfloat2a/softfloat-specialize.h
+++ b/fpu/softfloat2a/softfloat-specialize.h
@@ -686,6 +686,49 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag
bIsQNaN, flag bIsSNaN,
#endif
/*----------------------------------------------------------------------------
+| Takes two half-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float16 propagateFloat16NaN(float16 a, float16 b, float_status *status)
+{
+ flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
+ flag aIsLargerSignificand;
+ uint16_t av, bv;
+
+ aIsQuietNaN = float16_is_quiet_nan(a, status);
+ aIsSignalingNaN = float16_is_signaling_nan(a, status);
+ bIsQuietNaN = float16_is_quiet_nan(b, status);
+ bIsSignalingNaN = float16_is_signaling_nan(b, status);
+ av = float16_val(a);
+ bv = float16_val(b);
+
+ if (aIsSignalingNaN | bIsSignalingNaN) {
+ float_raise(float_flag_invalid, status);
+ }
+
+ if (status->default_nan_mode) {
+ return float16_default_nan(status);
+ }
+
+ if ((uint16_t)(av << 1) < (uint16_t)(bv << 1)) {
+ aIsLargerSignificand = 0;
+ } else if ((uint16_t)(bv << 1) < (uint16_t)(av << 1)) {
+ aIsLargerSignificand = 1;
+ } else {
+ aIsLargerSignificand = (av < bv) ? 1 : 0;
+ }
+
+ if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
+ aIsLargerSignificand)) {
+ return float16_maybe_silence_nan(b, status);
+ } else {
+ return float16_maybe_silence_nan(a, status);
+ }
+}
+
+/*----------------------------------------------------------------------------
| Takes two single-precision floating-point values `a' and `b', one of which
| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
| signaling NaN, the invalid exception is raised.
--
2.13.0
- Re: [Qemu-arm] [RFC PATCH for 2.11 13/23] target/arm/translate-a64.c: add FP16 FADD to AdvSIMD 3 Same, (continued)
- [Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/20
- Re: [Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Richard Henderson, 2017/07/20
- Re: [Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/21
- Re: [Qemu-arm] [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Aurelien Jarno, 2017/07/21
- Re: [Qemu-arm] [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/21
- Re: [Qemu-arm] [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Peter Maydell, 2017/07/21
- Re: [Qemu-arm] [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Aurelien Jarno, 2017/07/21
- Re: [Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/28
- Re: [Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Richard Henderson, 2017/07/28
[Qemu-arm] [RFC PATCH for 2.11 17/23] fpu/softfloat2a: implement propagateFloat16NaN,
Alex Bennée <=
[Qemu-arm] [RFC PATCH for 2.11 04/23] softfloat3c: fixup include paths, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 15/23] target/arm/translate-a64.c: AdvSIMD scalar 2 register misc decode, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 22/23] fpu/softfloat2a: improve comments on ARM NaN propagation, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 23/23] target/arm: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 18/23] fpu/softfloat2a: implement float16_squash_input_denormal, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 16/23] include/exec/helper-head.h: support f16 in helper calls, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 14/23] target/arm/translate-a64.c: add ARMv8.2 fadd scalar half-precision, Alex Bennée, 2017/07/20