Re: [Qemu-arm] [PATCH] ARM i.MX timers: fix software reset

[Peter Maydell]

On 17 February 2017 at 18:18, Kurban Mallachiev <address@hidden> wrote:
> Hello!
>
> i.MX6 RM says that setting software reset bit in CR register of GPT (general
> purpose timers) should resets all of the registers of GPT to their default
> reset values, except for the CLKSRC, EN, ENMOD, STOPEN, WAITEN, and DBGEN
> bits in CR. But current implementation does the opposite for CR register (it
> clears CLKSRC and friends bits and preserves the others).
>
> Most importantly this leads to that software reset bit doesn't clears
> automatically.
>
> I have a look at git history and found that software reset bit was being
> cleared before 462566fc5e3 commit.
>
> I have doubts about the correct fixing of this problem. I don't really
> understand the nature of the "Soft reset doesn't touch some bits; hard reset
> clears them" comment in imx_gpt_reset function, does it mean that
> imx_gpt_reset performs a hard reset or soft reset? I see two possible
> fixings:
>
> 1. If imx_gpt_reset purpose is to do a software reset of device, then we
> should fix this function. My patch at the end of email fixes this function.
>
> 2. If imx_gpt_reset purpose is to do a hard reset of device? then there
> should be another function to software reset of device. If so I can create a
> new patch.

As the function registered via the DeviceState's dc->reset
pointer, imx_gpt_reset() has to behave as a "device was
powercycled" level reset. It looks like we also call it
from imx_gpt_write() when the guest does a write to a
particular register. If that guest-requested reset has
to have different behaviour from "device was powered off
and on again" then it needs to use a different function
and can't just call imx_gpt_reset().

thanks
-- PMM