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[Qemu-arm] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs |
Date: |
Mon, 9 Jan 2017 16:05:06 +0000 |
This patchset adds support for the Virtualization extensions to QEMU's
GICv3 emulation. This was the last missing piece that was stopping
us from turning on the EL2 support in the CPU model, so the patchset
also adds support for enabling it all on the virt board via the
'-machine virtualization=on' option.
The result works well enough to allow booting a KVM outer guest kernel
and then running QEMU + an inner guest under KVM inside it. The outer
guest KVM also passes the kvm-unit-tests GIC tests.
Changes v1->v2:
* rebased on master; some of the earlier patches in v1
have now gone into master, as has Drew's ACPI cleanup set
* new patch "psci.c: If EL2 implemented, start CPUs in EL2"
fixes the problems with SMP configs not starting properly
* includes Drew's changes to report SMC vs HVC in ACPI
(slightly tweaked by me)
Patches 1, 4-13, 15, 16 still need review.
Git branch for this:
https://git.linaro.org/people/peter.maydell/qemu-arm.git gicv3-virt
thanks
-- PMM
Andrew Jones (1):
hw/arm/virt-acpi-build: use SMC if booting in EL2
Peter Maydell (17):
hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ
hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ
target-arm: Expose output GPIO line for VCPU maintenance interrupt
hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU
target-arm: Add ARMCPU fields for GIC CPU i/f config
hw/intc/gicv3: Add defines for ICH system register fields
hw/intc/gicv3: Add data fields for virtualization support
hw/intc/arm_gicv3: Add accessors for ICH_ system registers
hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors
hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers
hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR
hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()
hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs
hw/arm/virt: Support using SMC for PSCI
target/arm/psci.c: If EL2 implemented, start CPUs in EL2
target-arm: Enable EL2 feature bit on A53 and A57
hw/arm/virt: Add board property to enable EL2
hw/intc/gicv3_internal.h | 79 +++
include/hw/arm/virt.h | 5 +-
include/hw/intc/arm_gic_common.h | 2 +
include/hw/intc/arm_gicv3_common.h | 21 +
target/arm/cpu.h | 9 +
hw/arm/virt-acpi-build.c | 29 +-
hw/arm/virt.c | 87 ++-
hw/arm/xlnx-zynqmp.c | 2 +
hw/intc/arm_gic_common.c | 6 +
hw/intc/arm_gicv3_common.c | 31 +
hw/intc/arm_gicv3_cpuif.c | 1351 +++++++++++++++++++++++++++++++++++-
target/arm/cpu.c | 15 +
target/arm/cpu64.c | 8 +
target/arm/psci.c | 25 +-
hw/intc/trace-events | 33 +
15 files changed, 1642 insertions(+), 61 deletions(-)
--
2.7.4
- [Qemu-arm] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs,
Peter Maydell <=
- [Qemu-arm] [PATCH v2 09/18] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 14/18] hw/arm/virt: Support using SMC for PSCI, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 11/18] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 01/18] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 18/18] hw/arm/virt: Add board property to enable EL2, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 15/18] hw/arm/virt-acpi-build: use SMC if booting in EL2, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 17/18] target-arm: Enable EL2 feature bit on A53 and A57, Peter Maydell, 2017/01/09