Re: [Qemu-arm] Qemu-arm Digest, Vol 15, Issue 76

On Wed, Dec 21, 2016 at 4:48 AM, <address@hidden> wrote:

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Today's Topics:

1. Re: [Qemu-devel] [PATCH v4 0/7] q35: add negotiable broadcast
SMI (address@hidden)
2. [PATCH v3 0/3] Add the generic ARM timer (Alistair Francis)
3. [PATCH v3 1/3] arm_generic_timer: Add the ARM Generic Timer
(Alistair Francis)

----------------------------------------------------------------------

Message: 1
Date: Tue, 20 Dec 2016 15:01:17 -0800 (PST)
From: address@hidden
To: address@hidden
Cc: address@hidden, address@hidden, address@hidden,
address@hidden, address@hidden, address@hidden,
address@hidden, address@hidden, address@hidden,
address@hidden, address@hidden, address@hidden
Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v4 0/7] q35: add
negotiable broadcast SMI
Message-ID: <148227487620.73.10055858460424473693@790289a7ca88>
Content-Type: text/plain; charset="utf-8"

Hi,

Your series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v4 0/7] q35: add negotiable broadcast SMI
Message-id: 20161201170624.26496-1-lersek@redhat.com
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
>From https://github.com/patchew-project/qemu
- [tag update] patchew/1480926904-17596-1-git-send-email-zhang.address@hidden -> patchew/1480926904-17596-1-git-send-email-zhang.address@hidden
- [tag update] patchew/1481625384-15077-1-git-send-email-peter.maydell@linaro.org -> patchew/1481625384-15077-1-git-send-email-peter.maydell@linaro.org
- [tag update] patchew/1481856403-23599-1-git-send-email-zhangchen.fnst@cn.fujitsu.com -> patchew/1481856403-23599-1-git-send-email-zhangchen.fnst@cn.fujitsu.com
* [new tag] patchew/1482137486-9843-1-git-address@hiddenfujitsu.com -> patchew/1482137486-9843-1-git-address@hiddenfujitsu.com
* [new tag] patchew/1482140507-23607-1-git-send-email-vlad.lungu@windriver.com -> patchew/1482140507-23607-1-git-send-email-vlad.lungu@windriver.com
* [new tag] patchew/1482145554-88823-1-git-send-email-wei.w.wang@intel.com -> patchew/1482145554-88823-1-git-send-email-wei.w.wang@intel.com
* [new tag] patchew/1482156623-9111-1-git-address@hidden -> patchew/1482156623-9111-1-git-address@hidden
* [new tag] patchew/148215768690.13973.9042496691140000163.stgit@bahia -> patchew/148215768690.13973.9042496691140000163.stgit@bahia
* [new tag] patchew/1482158486-18597-1-address@hiddencom -> patchew/1482158486-18597-1-address@hiddencom
* [new tag] patchew/1482187106-85065-1-git-send-email-sochin.jiang@huawei.com -> patchew/1482187106-85065-1-git-send-email-sochin.jiang@huawei.com
* [new tag] patchew/1482255793-19057-1-git-send-email-ehabkost@redhat.com -> patchew/1482255793-19057-1-git-send-email-ehabkost@redhat.com
* [new tag] patchew/1482268300-10082-1-git-send-email-andrew.smirnov@gmail.com -> patchew/1482268300-10082-1-git-send-email-andrew.smirnov@gmail.com
* [new tag] patchew/1482268598-27422-1-address@hiddencom -> patchew/1482268598-27422-1-address@hiddencom
* [new tag] patchew/1482269164-14642-1-address@hidden -> patchew/1482269164-14642-1-address@hidden
* [new tag] patchew/20161201170624.26496-address@hidden -> patchew/20161201170624.26496-address@hidden
- [tag update] patchew/20161212224325.20790-address@hidden -> patchew/20161212224325.20790-address@hidden
- [tag update] patchew/20161214070156.23368-address@hidden -> patchew/20161214070156.23368-address@hidden
* [new tag] patchew/20161219205054.4677-1-address@hidden -> patchew/20161219205054.4677-1-address@hidden
* [new tag] patchew/20161220163139.12016-address@hidden -> patchew/20161220163139.12016-address@hidden
* [new tag] patchew/b0619e40-daca-9b28-address@hiddenorg -> patchew/b0619e40-daca-9b28-address@hiddenorg
* [new tag] patchew/cover.1482143215.git.address@hidden -> patchew/cover.1482143215.git.address@hidden
* [new tag] patchew/cover.1482164622.git.address@hidden -> patchew/cover.1482164622.git.address@hidden
* [new tag] patchew/cover.1482187052.git.address@hidden -> patchew/cover.1482187052.git.address@hidden
Switched to a new branch 'test'
2d2326b hw/i386/pc_q35: advertise broadcast SMI if VCPU hotplug is turned off
3443a68 hw/isa/lpc_ich9: add broadcast SMI feature
3863642 hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
12b2efd hw/i386/pc: introduce 2.9 machine types with 0x20 fw_cfg file slots
5387420 fw-cfg: expose "file_slots" parameter in fw_cfg_init_io_dma()
c550b2c fw-cfg: turn FW_CFG_FILE_SLOTS into a device property
1f40c84 fw-cfg: support writeable blobs

=== OUTPUT BEGIN ===
Checking PATCH 1/7: fw-cfg: support writeable blobs...
Checking PATCH 2/7: fw-cfg: turn FW_CFG_FILE_SLOTS into a device property...
Checking PATCH 3/7: fw-cfg: expose "file_slots" parameter in fw_cfg_init_io_dma()...
Checking PATCH 4/7: hw/i386/pc: introduce 2.9 machine types with 0x20 fw_cfg file slots...
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#126: FILE: include/hw/compat.h:4:
+#define HW_COMPAT_2_8 \
+ {\
+ .driver = "fw_cfg_mem",\
+ .property = "file_slots",\
+ .value = stringify(0x10),\
+ },{\
+ .driver = "fw_cfg_io",\
+ .property = "file_slots",\
+ .value = stringify(0x10),\
+ },

total: 1 errors, 0 warnings, 119 lines checked

Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 5/7: hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg...
Checking PATCH 6/7: hw/isa/lpc_ich9: add broadcast SMI feature...
Checking PATCH 7/7: hw/i386/pc_q35: advertise broadcast SMI if VCPU hotplug is turned off...
=== OUTPUT END ===

Test command exited with code: 1

---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden

------------------------------

Message: 2
Date: Tue, 20 Dec 2016 14:41:59 -0800
From: Alistair Francis <address@hidden>
To: <address@hidden>, <address@hidden>,
<address@hidden>, <address@hidden>
Cc: <address@hidden>, <address@hidden>
Subject: [Qemu-arm] [PATCH v3 0/3] Add the generic ARM timer
Message-ID: <cover.1482265908.git.address@hidden>
Content-Type: text/plain

These three patches and and connect the Generic ARM Timer. This includes
support for dropping insecure writes and includes the ReadBase memory
map.

V3:
- Add the ReadBase memory map
- Update the names to match the ARM ARM
V2:
- Fix couter/counter typo

Alistair Francis (3):
arm_generic_timer: Add the ARM Generic Timer
arm_generic_timer: Add support for the ReadBase memory map
xlnx-zynqmp: Connect the ARM Generic Timer

hw/arm/xlnx-zynqmp.c | 14 +++
hw/timer/Makefile.objs | 1 +
hw/timer/arm_generic_timer.c | 232 +++++++++++++++++++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 2 +
include/hw/timer/arm_generic_timer.h | 74 +++++++++++
5 files changed, 323 insertions(+)
create mode 100644 hw/timer/arm_generic_timer.c
create mode 100644 include/hw/timer/arm_generic_timer.h

--
2.7.4

------------------------------

Message: 3
Date: Tue, 20 Dec 2016 14:42:02 -0800
From: Alistair Francis <address@hidden>
To: <address@hidden>, <address@hidden>,
<address@hidden>, <address@hidden>
Cc: <address@hidden>, <address@hidden>
Subject: [Qemu-arm] [PATCH v3 1/3] arm_generic_timer: Add the ARM
Generic Timer
Message-ID:
<b985247bfcb7375de984e801c4145fde931360bb.1482265908.git.address@hidden>

Content-Type: text/plain

Add the ARM generic timer. This allows the guest to poll the timer for
values and also supports secure writes only.

Signed-off-by: Alistair Francis <address@hidden>
---
V3:
- Use ARM ARM names
- Indicate that we don't support all of the registers
- Fixup the Makefile CONFIG
V2:
- Fix couter/counter typo

hw/timer/Makefile.objs | 1 +
hw/timer/arm_generic_timer.c | 205 +++++++++++++++++++++++++++++++++++
include/hw/timer/arm_generic_timer.h | 62 +++++++++++
3 files changed, 268 insertions(+)
create mode 100644 hw/timer/arm_generic_timer.c
create mode 100644 include/hw/timer/arm_generic_timer.h

diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 7ba8c23..bb203e2 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -17,6 +17,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
+common-obj-$(CONFIG_ARM_TIMER) += arm_generic_timer.o

obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
diff --git a/hw/timer/arm_generic_timer.c b/hw/timer/arm_generic_timer.c
new file mode 100644
index 0000000..da434a7
--- /dev/null
+++ b/hw/timer/arm_generic_timer.c
@@ -0,0 +1,205 @@
+/*
+ * QEMU model of the ARM Generic Timer
+ *
+ * Copyright (c) 2016 Xilinx Inc.
+ * Written by Alistair Francis <address@hidden>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/timer/arm_generic_timer.h"
+#include "qemu/timer.h"
+#include "qemu/log.h"
+
+#ifndef ARM_GEN_TIMER_ERR_DEBUG
+#define ARM_GEN_TIMER_ERR_DEBUG 0
+#endif
+
+static void counter_control_postw(RegisterInfo *reg, uint64_t val64)
+{
+ ARMGenTimer *s = ARM_GEN_TIMER(reg->opaque);
+ bool new_status = extract32(s->regs[R_CNTCR],
+ R_CNTCR_EN_SHIFT,
+ R_CNTCR_EN_LENGTH);
+ uint64_t current_ticks;
+
+ current_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
+ NANOSECONDS_PER_SECOND, 1000000);
+
+ if ((s->enabled && !new_status) ||
+ (!s->enabled && new_status)) {
+ /* The timer is being disabled or enabled */
+ s->tick_offset = current_ticks - s->tick_offset;
+ }
+
+ s->enabled = new_status;
+}
+
+static uint64_t counter_value_postr(RegisterInfo *reg)
+{
+ ARMGenTimer *s = ARM_GEN_TIMER(reg->opaque);
+ uint64_t current_ticks, total_ticks;
+
+ if (s->enabled) {
+ current_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
+ NANOSECONDS_PER_SECOND, 1000000);
+ total_ticks = current_ticks - s->tick_offset;
+ } else {
+ /* Timer is disabled, return the time when it was disabled */
+ total_ticks = s->tick_offset;
+ }
+
+ return total_ticks;
+}
+
+static uint64_t counter_low_value_postr(RegisterInfo *reg, uint64_t val64)
+{
+ return (uint32_t) counter_value_postr(reg);
+}
+
+static uint64_t counter_high_value_postr(RegisterInfo *reg, uint64_t val64)
+{
+ return (uint32_t) (counter_value_postr(reg) >> 32);
+}
+
+static RegisterAccessInfo arm_gen_timer_regs_info[] = {
+ { .name = "CNTCR",
+ .addr = A_CNTCR,
+ .rsvd = 0xfffffffc,
+ .post_write = counter_control_postw,
+ },{ .name = "CNTSR",
+ .addr = A_CNTSR,
+ .rsvd = 0xfffffffd, .ro = 0x2,
+ },{ .name = "CNTCV_LOWER",
+ .addr = A_CNTCV_LOWER,
+ .post_read = counter_low_value_postr,
+ },{ .name = "CNTCV_UPPER",
+ .addr = A_CNTCV_UPPER,
+ .post_read = counter_high_value_postr,
+ },{ .name = "CNTFID0",
+ .addr = A_CNTFID0,
+ }
+ /* We don't model CNTFIDn */
+ /* We don't model the CounterID registers either */
+};
+
+static void arm_gen_timer_reset(DeviceState *dev)
+{
+ ARMGenTimer *s = ARM_GEN_TIMER(dev);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+
+ s->tick_offset = 0;
+ s->enabled = false;
+}
+
+static MemTxResult arm_gen_timer_read(void *opaque, hwaddr addr,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ /* Reads are always supported, just blindly pass them through */
+ *data = "" addr, size);
+
+ return MEMTX_OK;
+}
+
+static MemTxResult arm_gen_timer_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size,
+ MemTxAttrs attrs)
+{
+ /* Block insecure writes */
+ if (!attrs.secure) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Non secure writes to the system timestamp generator " \
+ "are invalid\n");
+ return MEMTX_ERROR;
+ }
+
+ register_write_memory(opaque, addr, data, size);
+
+ return MEMTX_OK;
+}
+
+static const MemoryRegionOps arm_gen_timer_ops = {
+ .read_with_attrs = arm_gen_timer_read,
+ .write_with_attrs = arm_gen_timer_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static const VMStateDescription vmstate_arm_gen_timer = {
+ .name = TYPE_ARM_GEN_TIMER,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, ARMGenTimer, R_ARM_GEN_TIMER_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void arm_gen_timer_init(Object *obj)
+{
+ ARMGenTimer *s = ARM_GEN_TIMER(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+
+ memory_region_init_io(&s->iomem, obj, &arm_gen_timer_ops, s,
+ TYPE_ARM_GEN_TIMER, R_ARM_GEN_TIMER_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), arm_gen_timer_regs_info,
+ ARRAY_SIZE(arm_gen_timer_regs_info),
+ s->regs_info, s->regs,
+ &arm_gen_timer_ops,
+ ARM_GEN_TIMER_ERR_DEBUG,
+ R_ARM_GEN_TIMER_MAX * 4);
+ memory_region_add_subregion(&s->iomem,
+ A_CNTCR,
+ &reg_array->mem);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void arm_gen_timer_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = arm_gen_timer_reset;
+ dc->vmsd = &vmstate_arm_gen_timer;
+}
+
+static const TypeInfo arm_gen_timer_info = {
+ .name = TYPE_ARM_GEN_TIMER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(ARMGenTimer),
+ .class_init = arm_gen_timer_class_init,
+ .instance_init = arm_gen_timer_init,
+};
+
+static void arm_gen_timer_register_types(void)
+{
+ type_register_static(&arm_gen_timer_info);
+}
+
+type_init(arm_gen_timer_register_types)
diff --git a/include/hw/timer/arm_generic_timer.h b/include/hw/timer/arm_generic_timer.h
new file mode 100644
index 0000000..ae4319c
--- /dev/null
+++ b/include/hw/timer/arm_generic_timer.h
@@ -0,0 +1,62 @@
+/*
+ * QEMU model of the ARM Generic Timer
+ *
+ * Copyright (c) 2016 Xilinx Inc.
+ * Written by Alistair Francis <address@hidden>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef ARM_GEN_TIMER_H
+#define ARM_GEN_TIMER_H
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+
+#define TYPE_ARM_GEN_TIMER "arm.generic-timer"
+#define ARM_GEN_TIMER(obj) \
+ OBJECT_CHECK(ARMGenTimer, (obj), TYPE_ARM_GEN_TIMER)
+
+REG32(CNTCR, 0x00)
+ FIELD(CNTCR, EN, 0, 1)
+ FIELD(CNTCR, HDBG, 1, 1)
+REG32(CNTSR, 0x04)
+ FIELD(CNTSR, DBGH, 1, 1)
+REG32(CNTCV_LOWER, 0x08)
+REG32(CNTCV_UPPER, 0x0C)
+REG32(CNTFID0, 0x20)
+/* We don't model CNTFIDn */
+/* We don't model the CounterID registers either */
+
+#define R_ARM_GEN_TIMER_MAX (R_CNTFID0 + 1)
+
+typedef struct ARMGenTimer {
+ /* <private> */
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+
+ /* <public> */
+ bool enabled;
+ uint64_t tick_offset;
+
+ uint32_t regs[R_ARM_GEN_TIMER_MAX];
+ RegisterInfo regs_info[R_ARM_GEN_TIMER_MAX];
+} ARMGenTimer;
+
+#endif
--
2.7.4

------------------------------

Subject: Digest Footer

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------------------------------

End of Qemu-arm Digest, Vol 15, Issue 76
****************************************

From:	Smrithi Cn
Subject:	Re: [Qemu-arm] Qemu-arm Digest, Vol 15, Issue 76
Date:	Wed, 21 Dec 2016 15:06:44 +0530