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[Qemu-arm] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_u
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update() |
Date: |
Tue, 13 Dec 2016 10:36:20 +0000 |
Implement the function which signals virtual interrupts to the
CPU as appropriate following CPU interface state changes.
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/intc/arm_gicv3_common.h | 1 +
hw/intc/arm_gicv3_cpuif.c | 49 ++++++++++++++++++++++++++++++++++++++
hw/intc/trace-events | 2 ++
3 files changed, 52 insertions(+)
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_common.h
index 665d3f8..4156051 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -150,6 +150,7 @@ struct GICv3CPUState {
qemu_irq parent_fiq;
qemu_irq parent_virq;
qemu_irq parent_vfiq;
+ qemu_irq maintenance_irq;
/* Redistributor */
uint32_t level; /* Current IRQ level */
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index f3845a6..e05f6b3 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -352,6 +352,53 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState
*cs)
static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
{
+ /* Tell the CPU about any pending virtual interrupts or
+ * maintenance interrupts, following a change to the state
+ * of the CPU interface relevant to virtual interrupts.
+ *
+ * CAUTION: this function will call qemu_set_irq() on the
+ * CPU maintenance IRQ line, which is typically wired up
+ * to the GIC as a per-CPU interrupt. This means that it
+ * will recursively call back into the GIC code via
+ * gicv3_redist_set_irq() and thus into the CPU interface code's
+ * gicv3_cpuif_update(). It is therefore important that this
+ * function is only called as the final action of a CPU interface
+ * register write implementation, after all the GIC state
+ * fields have been updated. gicv3_cpuif_update() also must
+ * not cause this function to be called, but that happens
+ * naturally as a result of there being no architectural
+ * linkage between the physical and virtual GIC logic.
+ */
+ int idx;
+ int irqlevel = 0;
+ int fiqlevel = 0;
+ int maintlevel = 0;
+
+ idx = hppvi_index(cs);
+ trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx);
+ if (idx >= 0) {
+ uint64_t lr = cs->ich_lr_el2[idx];
+
+ if (icv_hppi_can_preempt(cs, lr)) {
+ /* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */
+ if (lr & ICH_LR_EL2_GROUP) {
+ irqlevel = 1;
+ } else {
+ fiqlevel = 1;
+ }
+ }
+ }
+
+ if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) {
+ maintlevel = maintenance_interrupt_state(cs);
+ }
+
+ trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,
+ irqlevel, maintlevel);
+
+ qemu_set_irq(cs->parent_vfiq, fiqlevel);
+ qemu_set_irq(cs->parent_virq, irqlevel);
+ qemu_set_irq(cs->maintenance_irq, maintlevel);
}
static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -2480,6 +2527,8 @@ void gicv3_init_cpuif(GICv3State *s)
&& cpu->gic_num_lrs) {
int j;
+ cs->maintenance_irq = cpu->gicv3_maintenance_interrupt;
+
cs->num_list_regs = cpu->gic_num_lrs;
cs->vpribits = cpu->gic_vpribits;
cs->vprebits = cpu->gic_vprebits;
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 1dcc830..6116df5 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -138,6 +138,8 @@ gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val)
"GICv3 ICV_HPPIR%d rea
gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu %x
value 0x%" PRIx64
gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read
cpu %x value 0x%" PRIx64
gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d
write cpu %x value 0x%" PRIx64
+gicv3_cpuif_virt_update(uint32_t cpuid, int idx) "GICv3 CPU i/f %x virt HPPI
update LR index %d"
+gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel, int
maintlevel) "GICv3 CPU i/f %x virt HPPI update: setting FIQ %d IRQ %d
maintenance-irq %d"
# hw/intc/arm_gicv3_dist.c
gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure)
"GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure
%d"
--
2.7.4
- [Qemu-arm] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 17/23] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 14/23] hw/intc/gicv3: Add data fields for virtualization support, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(),
Peter Maydell <=
- [Qemu-arm] [PATCH 16/23] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 21/23] hw/arm/virt: Support using SMC for PSCI, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 13/23] hw/intc/gicv3: Add defines for ICH system register fields, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 15/23] hw/intc/arm_gicv3: Add accessors for ICH_ system registers, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 08/23] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 11/23] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 23/23] hw/arm/virt: Add board property to enable EL2, Peter Maydell, 2016/12/13