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[Qemu-arm] [PATCH v2 1/2] gic: provide defines for v2/v3 targetlist size
From: |
Andrew Jones |
Subject: |
[Qemu-arm] [PATCH v2 1/2] gic: provide defines for v2/v3 targetlist sizes |
Date: |
Fri, 1 Jul 2016 15:02:08 +0200 |
Signed-off-by: Andrew Jones <address@hidden>
---
include/hw/intc/arm_gic.h | 3 +++
include/hw/intc/arm_gicv3_common.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index 0971e37710dd6..42bb535fd4571 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -23,6 +23,9 @@
#include "arm_gic_common.h"
+/* Number of SGI target-list bits */
+#define GIC_TARGETLIST_BITS 8
+
#define TYPE_ARM_GIC "arm_gic"
#define ARM_GIC(obj) \
OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_common.h
index f72e49922feb1..341a3118f0f44 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -35,6 +35,9 @@
#define GICV3_MAXIRQ 1020
#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
+/* Number of SGI target-list bits */
+#define GICV3_TARGETLIST_BITS 16
+
/* Minimum BPR for Secure, or when security not enabled */
#define GIC_MIN_BPR 0
/* Minimum BPR for Nonsecure when security is enabled */
--
2.7.4