Re: [Qemu-arm] [Qemu-devel] [PATCH v2] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR

[Peter Maydell]

On 1 March 2016 at 19:58, Sergey Fedorov <address@hidden> wrote:
> On 01.03.2016 20:42, Peter Maydell wrote:
>>
>> The GICv2 introduces a new CPU interface register GICC_DIR, which
>> allows an OS to split the "priority drop" and "deactivate interrupt"
>> parts of interrupt completion. Implement this register.
>> (Note that the register is at offset 0x1000 in the CPU interface,
>> which means it is on a different 4K page from all the other registers.)
>>
>> Signed-off-by: Peter Maydell <address@hidden>

>> +static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs
>> attrs)
>> +{
>> +    int cm = 1 << cpu;
>> +    int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
>
>
> Looks like we don't have to check for gic_has_groups() here, because there
> is no way to set the interrupt group to 1, if gic_has_groups() is not true.

True, but we don't generally seem to rely on it -- this is just
the same line that was already present in gic_complete_irq().

> Anyway,
>
> Reviewed-by: Sergey Fedorov <address@hidden>

Thanks.

-- PMM