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Re: [Qemu-arm] [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 sy
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register |
Date: |
Mon, 18 Jan 2016 16:05:36 +0000 |
Oops, got the qemu-arm email address wrong...
On 18 January 2016 at 15:53, Peter Maydell <address@hidden> wrote:
> The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3,
> and allows those exception levels to read and write the FPEXC
> register for a lower exception level that is using AArch32.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> ARM Trusted Firmware expects this to exist (as does your average
> hypervisor, I expect).
>
> target-arm/helper.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 196c111..e8ede3f 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2890,6 +2890,17 @@ static void sctlr_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> tlb_flush(CPU(cpu), 1);
> }
>
> +static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo
> *ri)
> +{
> + if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + if (env->cp15.cptr_el[3] & CPTR_TFP) {
> + return CP_ACCESS_TRAP_EL3;
> + }
> + return CP_ACCESS_OK;
> +}
> +
> static const ARMCPRegInfo v8_cp_reginfo[] = {
> /* Minimal set of EL0-visible registers. This will need to be expanded
> * significantly for system emulation of AArch64 CPUs.
> @@ -3150,6 +3161,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
> .type = ARM_CP_NO_RAW,
> .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
> + { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
> + .type = ARM_CP_ALIAS,
> + .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
> + .access = PL2_RW, .accessfn = fpexc32_access },
> REGINFO_SENTINEL
> };
>
> --
> 1.9.1
>
thanks
-- PMM
- Re: [Qemu-arm] [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register,
Peter Maydell <=