diff -ur alsa-driver-virgin/pci/au88x0/au8810.h alsa-driver/pci/au88x0/au8810.h --- alsa-driver-virgin/pci/au88x0/au8810.h 2003-03-30 16:52:07.000000000 -0500 +++ alsa-driver/pci/au88x0/au8810.h 2003-04-01 15:10:07.000000000 -0500 @@ -9,7 +9,7 @@ */ - +#define AU8810_CHIP #define hwread(x,y) readl((x)+((y)>>2)) #define hwwrite(x,y,z) writel((z),(x)+((y)>>2)) @@ -18,30 +18,38 @@ #define NR_WT 0x40 /* ADBDMA */ -#define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */ +#define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */ #define POS_MASK 0x00000fff #define POS_SHIFT 0x0 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ -#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */ -#define VORTEX_ADBDMA_CTRL 0x10580 /* write only, format, flags, DMA pos */ +#define ADB_SUBBUF_SHIFT 0xc /* only. */ +#define VORTEX_ADBDMA_CTRL 0x27a00 /* write only; format, flags, DMA pos */ #define OFFSET_MASK 0x00000fff #define OFFSET_SHIFT 0x0 #define IE_MASK 0x00001000 /* interrupt enable. */ #define IE_SHIFT 0xc -#define U_MASK 0x00002000 /* Unknown. If you know tell me. */ +#define U_MASK 0x00002000 /* Unknown. If you know, tell me. */ #define U_SHIFT 0xd #define FMT_MASK 0x0003c000 #define FMT_SHIFT 0xe // The masks and shift also work for the wtdma, if not specified otherwise. +#define VORTEX_ADBDMA_BUFCFG0 0x27100 +#define VORTEX_ADBDMA_BUFCFG1 0x27104 +#define VORTEX_ADBDMA_BUFBASE 0x27000 +#define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */ +#define VORTEX_ADBDMA_FIFO_CEILING 0x1613c +#define VORTEX_ADBDMA_FIFO_NUM 0xf +#define VORTEX_ADBDMA_FIFO_INIT_FLAGS 0x11000 +#define VORTEX_ADBDMA_FIFO_UNK 0x20 /* ADB */ -#define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */ -#define VORTEX_ADB_RTBASE 0x10800 -#define VORTEX_ADB_CHNBASE 0x1099c -#define ROUTE_MASK 0x3fff -#define SOURCE_MASK 0x3f80 -//#define DEST_MASK 0x7f -#define ADB_MASK 0x7f +#define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */ +#define VORTEX_ADB_RTBASE 0x28000 +#define VORTEX_ADB_CHNBASE 0x282b4 +#define ROUTE_MASK 0xffff +#define SOURCE_MASK 0x3f80 +#define ADB_MASK 0xff +#define ADB_SHIFT 0x8 #define ADB_MIX_MASK 0xf /* ADB address */ #define OFFSET_ADBDMA 0x00 @@ -52,36 +60,42 @@ /* WTDMA */ -#define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */ -#define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */ +#define VORTEX_WTDMA_CTRL 0x27fd8 /* format, DMA pos */ +#define VORTEX_WTDMA_STAT 0x27fd8 /* DMA subbuf, DMA pos */ #define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT) #define WT_SUBBUF_SHIFT 0x15 +#define VORTEX_WTDMA_BUFBASE 0x27000 +#define VORTEX_WTDMA_BUFCFG0 0x27fd0 +#define VORTEX_WTDMA_BUFCFG1 0x27fd4 +#define VORTEX_WTDMA_START 0x27b00 /* which subbuffer is first */ -/* WT */ +/* */ /* MIXER */ -#define VORTEX_MIXER_SR 0x9f00 -#define VORTEX_MIXER_CHNBASE 0x9e40 -#define VORTEX_MIXER_RTBASE 0x9e00 +#define VORTEX_MIXER_SR 0x21f00 +#define VORTEX_MIXER_CHNBASE 0x21e40 +#define VORTEX_MIXER_RTBASE 0x21e00 /* MIX */ -#define VORTEX_MIX_INVOL_A 0x9000 /* in? */ -#define VORTEX_MIX_INVOL_B 0x8000 /* out? */ -#define VORTEX_MIX_VOL_A 0x9800 -#define VORTEX_MIX_VOL_B 0x8800 -#define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */ +#define VORTEX_MIX_INVOL_A 0x21000 /* in? */ +#define VORTEX_MIX_INVOL_B 0x20000 /* out? */ +#define VORTEX_MIX_VOL_A 0x21800 +#define VORTEX_MIX_VOL_B 0x20800 +#define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */ #define VOL_MIN 0x80 /* Input volume when muted. */ #define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ /* SRC */ -#define VORTEX_SRCBLOCK_SR 0xccc0 -#define VORTEX_SRC_CHNBASE 0xcc40 -#define VORTEX_SRC_RTBASE 0xcc00 -#define VORTEX_SRC_SOURCE 0xccc4 -#define VORTEX_SRC_CONVRATIO 0xce40 -#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) +#define VORTEX_SRCBLOCK_SR 0x26cc0 +#define VORTEX_SRC_CHNBASE 0x26c40 +#define VORTEX_SRC_RTBASE 0x26c00 +#define VORTEX_SRC_SOURCE 0x26cc4 +#define VORTEX_SRC_CONVRATIO 0x26cc0 +#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */ +#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */ + /* ADB route translate helper */ #define ADB_DMA(x) (x) @@ -102,43 +116,43 @@ /* FIFO */ -#define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */ -#define VORTEX_FIFO_WTCTRL 0xf840 +#define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */ +#define VORTEX_FIFO_WTCTRL 0x16000 #define FIFO_RDONLY 0x00000001 #define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */ #define FIFO_VALID 0x00000010 #define FIFO_EMPTY 0x00000020 #define FIFO_U0 0x00001000 /* Unknown. */ -#define VORTEX_FIFO_ADBDATA 0xe000 -#define VORTEX_FIFO_WTDATA 0xe800 +#define VORTEX_FIFO_ADBDATA 0x14000 +#define VORTEX_FIFO_WTDATA 0x10000 /* FIFO software state constants. */ #define FIFO_STOP 0 #define FIFO_START 1 #define FIFO_PAUSE 2 /* CODEC */ -#define VORTEX_CODEC_CTRL 0x11984 -#define VORTEX_CODEC_EN 0x11990 -#define VORTEX_CODEC_CHN 0x11880 +#define VORTEX_CODEC_CTRL 0x29184 +#define VORTEX_CODEC_EN 0x29190 +#define VORTEX_CODEC_CHN 0x29080 #define VORTEX_CODEC_WRITE 0x00800000 #define VORTEX_CODEC_ADDSHIFT 16 #define VORTEX_CODEC_ADDMASK 0x7f0000 /* 0x000f0000*/ #define VORTEX_CODEC_DATSHIFT 0 #define VORTEX_CODEC_DATMASK 0xffff -#define VORTEX_CODEC_IO 0x11988 +#define VORTEX_CODEC_IO 0x29188 /* Sample timer */ #define VORTEX_SMP_TIME 0x11998 /* IRQ */ -#define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */ +#define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */ #define IRQ_FATAL 0x0001 #define IRQ_PARITY 0x0002 #define IRQ_PCMOUT 0x0020 /* ?? */ #define IRQ_TIMER 0x1000 #define IRQ_MIDI 0x2000 -#define VORTEX_CTRL 0x1280c +#define VORTEX_CTRL 0x2880c #define CTRL_MIDI_EN 0x00000001 #define CTRL_MIDI_PORT 0x00000060 #define CTRL_GAME_EN 0x00000008 @@ -153,11 +167,11 @@ #define IRQ_MIDI 0x2000 /* write: Timer period config / read: TIMER IRQ ack. */ -#define VORTEX_IRQ_STAT 0x1199c +#define VORTEX_IRQ_STAT 0x2919c /* DMA */ -#define VORTEX_DMA_BUFFER 0x10200 -#define VORTEX_ENGINE_CTRL 0x1060c +#define VORTEX_DMA_BUFFER 0x27000 +#define VORTEX_ENGINE_CTRL 0x27ae8 /* MIDI */ /* GAME. */ #define VORTEX_MIDI_DATA 0x11000 Only in alsa-driver/pci/au88x0: au8810.h.rej diff -ur alsa-driver-virgin/pci/au88x0/au8820.h alsa-driver/pci/au88x0/au8820.h --- alsa-driver-virgin/pci/au88x0/au8820.h 2003-03-30 16:52:07.000000000 -0500 +++ alsa-driver/pci/au88x0/au8820.h 2003-03-30 16:49:49.000000000 -0500 @@ -9,7 +9,7 @@ */ - +#define AU8820_CHIP #ifndef PCI_VENDOR_ID_AUREAL_VORTEX #define PCI_DEVICE_ID_AUREAL_VORTEX 0x0001 @@ -40,7 +40,10 @@ #define VORTEX_ADBDMA_BUFCFG1 0x10404 #define VORTEX_ADBDMA_BUFBASE 0x10200 #define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */ - +#define VORTEX_ADBDMA_FIFO_CEILING 0xf83c +#define VORTEX_ADBDMA_FIFO_NUM 0xf +#define VORTEX_ADBDMA_FIFO_INIT_FLAGS 0x11000 +#define VORTEX_ADBDMA_FIFO_UNK 0x20 /* ADB */ #define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */ @@ -67,6 +70,10 @@ #define VORTEX_WTDMA_BUFCFG0 0x10300 #define VORTEX_WTDMA_BUFCFG1 0x10304 #define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */ +#define VORTEX_WTDMA_FIFO_CEILING 0xf8bc +#define VORTEX_WTDMA_FIFO_NUM 0x3f +#define VORTEX_WTDMA_FIFO_INIT_FLAGS 0x1000 +#define VORTEX_WTDMA_FIFO_UNK 0x20 /* WT */ // Please disassemble asp4wt.vxd :) diff -ur alsa-driver-virgin/pci/au88x0/au8830.h alsa-driver/pci/au88x0/au8830.h --- alsa-driver-virgin/pci/au88x0/au8830.h 2003-03-30 16:52:07.000000000 -0500 +++ alsa-driver/pci/au88x0/au8830.h 2003-04-01 15:09:35.000000000 -0500 @@ -9,7 +9,7 @@ */ - +#define AU8830_CHIP #define hwread(x,y) readl((x)+((y)>>2)) #define hwwrite(x,y,z) writel((z),(x)+((y)>>2)) @@ -18,12 +18,12 @@ #define NR_WT 0x40 /* ADBDMA */ -#define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */ +#define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */ #define POS_MASK 0x00000fff #define POS_SHIFT 0x0 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ -#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */ -#define VORTEX_ADBDMA_CTRL 0x10580 /* write only; format, flags, DMA pos */ +#define ADB_SUBBUF_SHIFT 0xc /* only. */ +#define VORTEX_ADBDMA_CTRL 0x27a00 /* write only; format, flags, DMA pos */ #define OFFSET_MASK 0x00000fff #define OFFSET_SHIFT 0x0 #define IE_MASK 0x00001000 /* interrupt enable. */ @@ -33,14 +33,23 @@ #define FMT_MASK 0x0003c000 #define FMT_SHIFT 0xe // The masks and shift also work for the wtdma, if not specified otherwise. +#define VORTEX_ADBDMA_BUFCFG0 0x27800 +#define VORTEX_ADBDMA_BUFCFG1 0x27804 +#define VORTEX_ADBDMA_BUFBASE 0x27400 +#define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */ +#define VORTEX_ADBDMA_FIFO_CEILING 0x1617c +#define VORTEX_ADBDMA_FIFO_NUM 0x1f +#define VORTEX_ADBDMA_FIFO_INIT_FLAGS 0x42000 +#define VORTEX_ADBDMA_FIFO_UNK 0x40 /* ADB */ -#define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */ -#define VORTEX_ADB_RTBASE 0x10800 -#define VORTEX_ADB_CHNBASE 0x1099c -#define ROUTE_MASK 0x3fff +#define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */ +#define VORTEX_ADB_RTBASE 0x28000 +#define VORTEX_ADB_CHNBASE 0x282b4 +#define ROUTE_MASK 0xffff #define SOURCE_MASK 0x3f80 #define ADB_MASK 0xff +#define ADB_SHIFT 0x8 #define ADB_MIX_MASK 0xf /* ADB address */ #define OFFSET_ADBDMA 0x00 @@ -51,36 +60,46 @@ /* WTDMA */ -#define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */ -#define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */ +#define VORTEX_WTDMA_CTRL 0x27900 /* format, DMA pos */ +#define VORTEX_WTDMA_STAT 0x27900 /* DMA subbuf, DMA pos */ #define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT) #define WT_SUBBUF_SHIFT 0x15 +#define VORTEX_WTDMA_BUFBASE 0x27000 +#define VORTEX_WTDMA_BUFCFG0 0x27600 +#define VORTEX_WTDMA_BUFCFG1 0x27604 +#define VORTEX_WTDMA_START 0x27b00 /* which subbuffer is first */ +#define VORTEX_WTDMA_FIFO_CEILING 0x160fc +#define VORTEX_WTDMA_FIFO_NUM 0x3f +#define VORTEX_WTDMA_FIFO_INIT_FLAGS 0x42000 +#define VORTEX_WTDMA_FIFO_UNK 0x40 -/* WT */ +/* */ /* MIXER */ -#define VORTEX_MIXER_SR 0x9f00 -#define VORTEX_MIXER_CHNBASE 0x9e40 -#define VORTEX_MIXER_RTBASE 0x9e00 +#define VORTEX_MIXER_SR 0x21f00 +#define VORTEX_MIXER_CHNBASE 0x21e40 +#define VORTEX_MIXER_RTBASE 0x21e00 /* MIX */ -#define VORTEX_MIX_INVOL_A 0x9000 /* in? */ -#define VORTEX_MIX_INVOL_B 0x8000 /* out? */ -#define VORTEX_MIX_VOL_A 0x9800 -#define VORTEX_MIX_VOL_B 0x8800 -#define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */ +#define VORTEX_MIX_INVOL_A 0x21000 /* in? */ +#define VORTEX_MIX_INVOL_B 0x20000 /* out? */ +#define VORTEX_MIX_VOL_A 0x21800 +#define VORTEX_MIX_VOL_B 0x20800 +#define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */ #define VOL_MIN 0x80 /* Input volume when muted. */ #define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ /* SRC */ -#define VORTEX_SRCBLOCK_SR 0xccc0 -#define VORTEX_SRC_CHNBASE 0xcc40 -#define VORTEX_SRC_RTBASE 0xcc00 -#define VORTEX_SRC_SOURCE 0xccc4 -#define VORTEX_SRC_CONVRATIO 0xce40 -#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) +#define VORTEX_SRCBLOCK_SR 0x26cc0 +#define VORTEX_SRC_CHNBASE 0x26c40 +#define VORTEX_SRC_RTBASE 0x26c00 +#define VORTEX_SRC_SOURCE 0x26cc4 +#define VORTEX_SRC_CONVRATIO 0x26cc0 +#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */ +#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */ + /* ADB route translate helper */ #define ADB_DMA(x) (x) @@ -101,43 +120,43 @@ /* FIFO */ -#define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */ -#define VORTEX_FIFO_WTCTRL 0xf840 +#define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */ +#define VORTEX_FIFO_WTCTRL 0x16000 #define FIFO_RDONLY 0x00000001 #define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */ #define FIFO_VALID 0x00000010 #define FIFO_EMPTY 0x00000020 #define FIFO_U0 0x00001000 /* Unknown. */ -#define VORTEX_FIFO_ADBDATA 0xe000 -#define VORTEX_FIFO_WTDATA 0xe800 +#define VORTEX_FIFO_ADBDATA 0x14000 +#define VORTEX_FIFO_WTDATA 0x10000 /* FIFO software state constants. */ #define FIFO_STOP 0 #define FIFO_START 1 #define FIFO_PAUSE 2 /* CODEC */ -#define VORTEX_CODEC_CTRL 0x11984 -#define VORTEX_CODEC_EN 0x11990 -#define VORTEX_CODEC_CHN 0x11880 +#define VORTEX_CODEC_CTRL 0x29184 +#define VORTEX_CODEC_EN 0x29190 +#define VORTEX_CODEC_CHN 0x29080 #define VORTEX_CODEC_WRITE 0x00800000 #define VORTEX_CODEC_ADDSHIFT 16 #define VORTEX_CODEC_ADDMASK 0x7f0000 /* 0x000f0000*/ #define VORTEX_CODEC_DATSHIFT 0 #define VORTEX_CODEC_DATMASK 0xffff -#define VORTEX_CODEC_IO 0x11988 +#define VORTEX_CODEC_IO 0x29188 /* Sample timer */ #define VORTEX_SMP_TIME 0x11998 /* IRQ */ -#define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */ +#define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */ #define IRQ_FATAL 0x0001 #define IRQ_PARITY 0x0002 #define IRQ_PCMOUT 0x0020 /* ?? */ #define IRQ_TIMER 0x1000 #define IRQ_MIDI 0x2000 -#define VORTEX_CTRL 0x1280c +#define VORTEX_CTRL 0x2880c #define CTRL_MIDI_EN 0x00000001 #define CTRL_MIDI_PORT 0x00000060 #define CTRL_GAME_EN 0x00000008 @@ -152,20 +171,20 @@ #define IRQ_MIDI 0x2000 /* write: Timer period config / read: TIMER IRQ ack. */ -#define VORTEX_IRQ_STAT 0x1199c +#define VORTEX_IRQ_STAT 0x2919c /* DMA */ -#define VORTEX_DMA_BUFFER 0x10200 -#define VORTEX_ENGINE_CTRL 0x1060c +#define VORTEX_DMA_BUFFER 0x27400 +#define VORTEX_ENGINE_CTRL 0x27ae8 /* MIDI */ /* GAME. */ -#define VORTEX_MIDI_DATA 0x11000 -#define VORTEX_MIDI_CMD 0x11004 /* Write command / Read status */ -#define VORTEX_GAME_LEGACY 0x11008 -#define VORTEX_CTRL2 0x1100c +#define VORTEX_MIDI_DATA 0x28800 +#define VORTEX_MIDI_CMD 0x28804 /* Write command / Read status */ +#define VORTEX_GAME_LEGACY 0x28808 +#define VORTEX_CTRL2 0x2880c #define CTRL2_GAME_ADCMODE 0x40 -#define VORTEX_GAME_AXIS 0x11010 +#define VORTEX_GAME_AXIS 0x28810 #define AXIS_SIZE 4 #define AXIS_RANGE 0x1fff -/* End of au8810.h */ +/* End of au8830.h */ diff -ur alsa-driver-virgin/pci/au88x0/au88x0_core.c alsa-driver/pci/au88x0/au88x0_core.c --- alsa-driver-virgin/pci/au88x0/au88x0_core.c 2003-03-30 16:52:07.000000000 -0500 +++ alsa-driver/pci/au88x0/au88x0_core.c 2003-03-30 17:17:44.000000000 -0500 @@ -630,27 +630,34 @@ /* 48 DMA channels. */ /* 16 ADB DMA channels fifos. */ - addr = 0xf83c; - for (x = 0xf; x >= 0; x--) { - hwwrite(vortex->mmio, addr, 0x11000); - if (hwread(vortex->mmio, addr) != 0x11000) + addr = VORTEX_ADBDMA_FIFO_CEILING; + for (x = VORTEX_ADBDMA_FIFO_NUM; x >= 0; x--) { + hwwrite(vortex->mmio, addr, VORTEX_ADBDMA_FIFO_INIT_FLAGS); + if (hwread(vortex->mmio, addr) != VORTEX_ADBDMA_FIFO_INIT_FLAGS) printk("bad fifo reset!"); - vortex_fifo_clearadbdata(vortex, x, 0x20); + vortex_fifo_clearadbdata(vortex, x, VORTEX_ADBDMA_FIFO_UNK); addr -= 4; } - /* 32 WT DMA channels fifos. */ - addr = 0xf8bc; - for (x = 0x1f; x >= 0; x--) { - hwwrite(vortex->mmio, addr, 0x1000); - if (hwread(vortex->mmio, addr) != 0x1000) + addr = VORTEX_WTDMA_FIFO_CEILING; + for (x = VORTEX_WTDMA_FIFO_NUM; x >= 0; x--) { + hwwrite(vortex->mmio, addr, VORTEX_WTDMA_FIFO_INIT_FLAGS); + if (hwread(vortex->mmio, addr) != VORTEX_WTDMA_FIFO_INIT_FLAGS) printk("bad fifo reset!"); - vortex_fifo_clearwtdata(vortex, x, 0x20); + vortex_fifo_clearwtdata(vortex, x, VORTEX_WTDMA_FIFO_UNK); addr -= 4; } +#ifdef AU8810_CHIP +#error __9CAsp4FIFOP9CAsp4HwIO not implemented yet +#elif defined(AU8820_CHIP) //temp = ebp; // = 0 ? //hwwrite(dma->mmio, 0xf8c0, ((temp | 0x03 )&= 0xffffff83) | 0xd00); hwwrite(vortex->mmio, 0xf8c0, 0x0843); //0xd03 0xd6b +#elif defined(AU8830_CHIP) + hwwrite(vortex->mmio, 0x17000, 0x61); + hwwrite(vortex->mmio, 0x17004, 0x61); + hwwrite(vortex->mmio, 0x17008, 0x61); +#endif } void vortex_fifo_adbinitialize(vortex_t *vortex, int fifo, int j) {