Re: [lwip-users] Problem running lwip on cortex M7 with D cache enabled

[Jochen Strohbeck]

Thanks for your posts. I try to summarize what I got so far:

- RX/TX descriptors must be in non-cacheable memory to avoid race
conditions. Alignment and padding is not necessary (?)

- RX/TX buffers must be in non-cacheable memory or can be in cacheable
memory but require explicit cache clean/invalidate before/after GMAC
DMAs and buffers must be aligned and padded to multiple of cache line size.

Regarding the same70_gmac.c and lwip 1.4.1 code I am using:

- RX/TX descriptors, ptr to pbufs and tx buffers are in one huge struct
called "gmac_device". I can place the whole struct to non-cacheable
memory. No need for alignment and padding. This should work for TX too.
Drawback is that there are harsh restrictions for non-cacheable memory
size which cannot be freely choosen and adapted to required size of the
struct.

- RX buffers are 'embedded' in s.c. pbufs and are allocated dynamically
in the lwip pool. Current code does not provide the required alignment
and padding as required for cache management.

- lwip 2.03 provides support for user defined pbufs which can be adapted
to support alignment and padding for cache management (?)

- cache clean/invalidate of RX buffer must be implemented for cache
management

This sounds complicated to me. Therefore my first and probably stupid
idea was to use explicit RX buffers, place them in non-cacheable memory
and use them for RX payload instead of an allocated buffer. Does this
probably work ?

Regards,
Jochen

goldsimon:
> 
> 
> Jan Menzel wrote:
>> I'd suggest to align (position and size) all receive
>> buffers to d-cache lines so that invalidation does not cause any side
>> effects.
> 
> And it's exactly this that lwip does not fully support yet. It doesn't work 
> for the tx side at all and for the rx side, we only have the workaraound with 
> custom pbufs (see the link Dirk posted).
> 
> Simon
> 
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