lwip-users
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [lwip-users] LPC1768 lpc_low_level_input: Packet dropped witherrors


From: Jan Menzel
Subject: Re: [lwip-users] LPC1768 lpc_low_level_input: Packet dropped witherrors (0xffffffff)
Date: Sat, 29 Nov 2014 11:37:43 +0100
User-agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0

Hi Paul!
        It seems that at least on the 1768 the descriptors and buffers have to
be located in the same block. This fixed my problem....

        Jan

On 28.11.2014 21:02, Paul Webber wrote:
> I just finished implimenting 1.41 on the LPC 4078 using parts of the NXP 
> examples. The DMA for the MAC works only with the 32K (in the LPC 4078) 
> block. I used the linker file to make sure nothing else ended up in that 
> memory block. Also if you are using the example provided by NXP there are 
> other things in that memory block, descriptors for the DMA and extra buffers.
> 
> Paul
> 
> ________________________________________
> From: address@hidden <address@hidden> on behalf of Simon Goldschmidt 
> <address@hidden>
> Sent: Friday, November 28, 2014 4:03 AM
> To: address@hidden
> Subject: Re: [lwip-users] LPC1768 lpc_low_level_input: Packet dropped 
> witherrors (0xffffffff)
> 
> Jan Menzel wrote:
>> On 28.11.2014 03:07, Grzegorz Niemirowski wrote:
>>> Does your low level driver use DMA? Is AHB-SRAM accessible by DMA?
>>>
>> Yes, all memory is accessible via DMA. IIRC datasheet says that flash
>> can not be used with EMAC.
> 
> I don't know the LPC1768, but a quick look at the LPC1769/68/67/66/65/64/63 
> Datasheet brings up this:
> 
> --- snip ---
> On-chip SRAM includes:
> -  32/16 kB of SRAM on the CPU with local code/data bus for high-performance 
> CPU access.
> -  Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
>    These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as
>    for general purpose CPU instruction and data storage.
> --- snap ---
> 
> To me, this implies the first SRAM block is for CPU-only storage (like stack, 
> state info, etc) and cannot be used for DMA.
> 
> 
> Simon
> 
> _______________________________________________
> lwip-users mailing list
> address@hidden
> https://lists.nongnu.org/mailman/listinfo/lwip-users
> 
> _______________________________________________
> lwip-users mailing list
> address@hidden
> https://lists.nongnu.org/mailman/listinfo/lwip-users
> 




reply via email to

[Prev in Thread] Current Thread [Next in Thread]