RE: [lwip-users] Problem With dns.c Using 32-Bit Compilers

[Grubb, Jared]

"Byte access is terribly inefficient for C on ARM" is not true. ARM/Thumb can 
access a byte with exactly one instruction (just like every instruction) and 
STRB takes exactly the same number of clock cycles to process as STR or STRH.

The only possible way that you could have byte-access take longer is if the ARM 
is hooked up to a memory bus that has a very strict word access requirement; in 
that case, the chip maker/FPGA programmer MUST insert special digital logic to 
adapt the ARM to that kind of bus. In that case, the reads would be cheap, but 
a write might require a "read-mask-write" operation that could induce extra 
memory wait states back to the ARM.

But even in that case, the problem is due to the memory architecture of the 
system, and has nothing to do with the ARM processor or the C language. As a 
counter-example, I could hook an ARM7 up to an 8-bit DRAM chip, and now byte 
access is four times FASTER than word access.

Jared

-----Original Message-----
From: address@hidden [mailto:address@hidden On Behalf Of Alain M.
Sent: Tuesday, September 02, 2008 12:24
To: Mailing list for lwIP users
Subject: Re: [lwip-users] Problem With dns.c Using 32-Bit Compilers


Grubb, Jared escreveu:
> I'm working with a ARM7TDMI and it definitely has byte access (the STRB 
> instruction, for example). The only case where the ARM7 could have trouble is 
> if it tries to access something (a word via STR, for example) at a 
> non-aligned boundary.

I didn't say that it does not have byte access, just that it is terribly
ineficient for a normal C program... This has been improved in r5 and Cortex

Alain