Re: [lwip-users] Lwip ARP problems

[dannylum]

I actually read on some other forum that this other person had a
similar problem and corrected by doing a ping to the FPGA before the
FPGA requests for a connection the PC. I applied this same approach
and it now works for me.

Looking at debug Lwip printouts from he FPGA shows that IP packets are
sent from the FPGA but no replies are coming back. However, Ethereal
captures on the PC show that FPGA ARP broadcasts are received and
replies are generated but immediately after PC replies back with its
MAC address, the FPGA sends another broadcast message.

As mentioned before, my temporary workaround was to introduce a delay
in the FPGA before connecting so just after sockets are all setup, I
would use the PC and ping the FPGA. Replies are received on PC side
and when the delay/sleep on FPGA elapses, it would connect succesfully
because the initial ping requests helped establish the ARP tables on
both sides (PC and FPGA).

Is this a problem with LWIP Xilinx port??? Although this works around
the problem at the moment, I would like to be able to hard code the
ARP entry for the PC since I will be using this project for a LAN only
so all MACs are known ahead of time. Are there any commands available
to achieve this given that I am using the BSD style API sockets.

I am reluctant to switch to Raw API in this stage of the game partly
because the deadline is fast approaching (approx 1/2 month).

Any hints or suggestions are much appreciated.

Thanks again guys,

Danny


dannylum wrote:
> 
> Hey guys,
> 
> I am a first time user of LWIP and using it for a 4th year project. I've
> been racking my brain for the past few days trying to figure out what's
> going on with LWIP...
> Basically I am running on a virtex2 board (xilinx multimedia) with LWIP
> and Xilkernel OS. The mode of operation is Sockets API (BSD style)  I have
> setup everything according to a reference webserver for another board. I
> have tested it and proven that using the FPGA as a webserver, we are able
> to accept connections from a PC via crossover cable. 
> 
> The problem I am facing is trying to use FPGA as client and connect to a
> server running on the PC.
> The code is pretty much identical but instead of using listen and accept I
> change it to use connect and setup the address stuff to reflect the
> server.
> 
> When I run this on the board with Ethereal open, I only see continous ARP
> packets being sent with the board MAC address requesting for the MAC of
> the PC using the PC's IP address. The PC replies and the FPGA again sends
> another broadcast out. This goes on for about 10 iterations when the
> connect procedure I guess times out and exits. The strange part is when I
> force it to retry again and again, after maybe 10 iterations of CONNECT
> timing out, it would connect. Sometimes when I'm lucky this would connect
> on the first go. Sometimes after 4 cycles of connect timeouts it would
> finally connect and I would see TCP packets going in Ethereal.
> 
> I have a feeling this can be a timing issue because it seems like after
> the FPGA sends an ARP request, the PC replies but the FPGA doesn't pick it
> up or something and again requests. After many cycles of this happening,
> it would work suddenly suggesting maybe at that correct "moment" the FPGA
> does see the reply from PC and adds the PC's MAC to its own ARP table.....
> 
> Any help is much appreciated...
> 
> Thanks in advance :)
> 
> Danny
> 

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