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RE: [lwip-users] Porting lwIP to MPC5200

From: Amir Bukhari
Subject: RE: [lwip-users] Porting lwIP to MPC5200
Date: Wed, 26 Oct 2005 16:04:01 +0200

I have some issue with getting FEC to work. I have configured SDMA
(Bestcomm) on MPC5200 to receive ethernet packet. I got the SDMA interrupt
for receiving but the buffer which should store the frame data is always
I can't find why this, does my FEC receive zero packet???
The packet -I receive- length is always 64 byte (icmp).

I will be thank if anyone has ported MPC5200 to lwip can help me getting

Here is a part of the SDMA interrupt handler:

if (TaskIntStatus(rxTaskId) == rxTaskId ) // FEC TaskID
        // get current BD
          TaskBD1_t *bd = (TaskBD1_t*) TaskGetBD(rxTaskId, rxBdPtr);
         * Clear the task interrupt.
        TaskIntClear( rxTaskId );
          // multiple RX frames can be hidden after this interrupt
          while(!(bd->Status & (1<<SDMA_BD_BIT_READY)))
                    sdma_callback_input((uint8 *)bd->DataPtr[0],
(uint16)(bd->Status & 0xFFFF));
             * Finished with the buffer descriptor.
            rxBdPtr = TaskBDRelease( rxTaskId );
             * Assign a new, empty buffer to the RX ring.
            TaskBDAssign( rxTaskId,
                NULL, RXBUFFLEN, 0);
            bd = (TaskBD1_t *)TaskGetBD( rxTaskId, rxBdPtr );

Here also my configuration for FEC
    FEC Configuration
    Physical Address: 00D09306C525
    Ethernet Interface: 18-wire 10/100 Mb/s mode
    RX Duplex Mode: Full Duplex (Receiver operates independently on Tx)
    TX Full Duplex mode (ignore Carrier Sense and Collision inputs): No 
    Flow Control Enable (detect & process 'Pause' frames): No 
    Perform Heartbeat check after each transmission: No 
    Internal Loopback Mode: Disabled
    Maximum Frame Length: 1518
    Promiscuous mode (receive everything): Yes
    Reject Broadcast frames: No 
    Heartbeat Error Interrupt: Enabled 
    Babbling Receiver Interrupt: Enabled 
    Babbling Transmitter Interrupt: Enabled 
    Graceful Stop Interrupt: Enabled 
    Transmit Frame Interrupt: Enabled 
    MII Interrupt Enable: Disabled
    Late Collision Enable: Enabled 
    Collision Retry Limit Interrupt: Enabled 
    TX FIFO Underrun Interrupt: Enabled 
    TX FIFO Error Interrupt: Enabled 
    RX FIFO Error Interrupt: Enabled
#define FEC_ECNTRL_INIT                   0x00100001
#define FEC_X_CNTRL_INIT                  0x00000000
#define FEC_R_CNTRL_INIT                  0x05EE000C
#define FEC_IMASK_INIT                    0xF83E0000
#define FEC_PADDR1_INIT                   0x00D09306
#define FEC_PADDR2_INIT                   0xC5258808
#define FEC_MII_PHY_ADDR                  0x00
#define FEC_ECNTRL_INIT                   0x00100001
#define FEC_X_CNTRL_INIT                  0x00000000
#define FEC_R_CNTRL_INIT                  0x05EE0004
#define FEC_IMASK_INIT                    0xF83E0000
#define FEC_PADDR1_INIT                   0x00D09306
#define FEC_PADDR2_INIT                   0xC5258808
#define FEC_MII_PHY_ADDR                  0x00
#define FEC_MII_SPEED_INIT                0x0000001C
#define FEC_PHY_DO_SETUP                  1
#define FEC_PHY_CONTROL_INIT              0x3100
#define FEC_PHY_ANADV_INIT                0x0101
#define FEC_PHY_WAIT_AN_DONE              1
#define FEC_PHY_CUSTOMCTL0                0x00141422
#define FEC_MIB_DO_CLEAR                  128
#define FEC_XMIT_FSM_INIT                 0x03000000

    FEC Configuration
    TX FIFO Watermark Level: 256 bytes 
    TX FIFO Granularity    : Full - 28 bytes 
    TX FIFO Alarm Level    : 0
    RX FIFO Granularity    : FIFO Empty 
    RX FIFO Alarm Level    : 800
#define FEC_X_WMRK_INIT                   0x00000003
#define FEC_RFIFO_CNTRL_INIT              0x00000000
#define FEC_RFIF0_ALARM_INIT              0x00000320
#define FEC_TFIFO_CNTRL_INIT              0x0F000000

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