[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[PATCH 2/6] arm: Force RES0 bits in TST/A1 to be 0

From: Kim Kuparinen
Subject: [PATCH 2/6] arm: Force RES0 bits in TST/A1 to be 0
Date: Sat, 20 Nov 2021 13:13:23 +0200

make check failed on quemu-system-arm when not using thumb with

'Illegal instruction'

apparently because bits marked RES0 in the arm spec were being set to random
According to the spec this leads to unpredictable behaviour:

Page 4356 for a description of reserved bits and page 5203 for the TST

Signed-off-by: Kim Kuparinen <>
 lib/jit_arm-cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/jit_arm-cpu.c b/lib/jit_arm-cpu.c
index b6ee260..f0f5111 100644
--- a/lib/jit_arm-cpu.c
+++ b/lib/jit_arm-cpu.c
@@ -612,7 +612,7 @@ static void _torl(jit_state_t*,int,int,int) maybe_unused;
 #  define CMNI(rn,im)                  CC_CMNI(ARM_CC_AL,rn,im)
 #  define T2_CMNI(rn,im)               torri(THUMB2_CMNI,rn,_R15_REGNO,im)
 #  define CC_TST(cc,rn,rm)             corrr(cc,ARM_TST,rn,r0,rm)
-#  define TST(rn,rm)                   CC_TST(ARM_CC_AL,rn,rm)
+#  define TST(rn,rm)                   corrr(ARM_CC_AL,ARM_TST,rn,0,rm)
 #  define T1_TST(rn,rm)                        
 #  define T2_TST(rn,rm)                        
 #  define CC_TSTI(cc,rn,im)            corri(cc,ARM_TST|ARM_I,rn,0,im)

reply via email to

[Prev in Thread] Current Thread [Next in Thread]