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Re: L4-hurd discuss

From: Espen Skoglund
Subject: Re: L4-hurd discuss
Date: Wed, 22 Jun 2005 19:56:53 +0200

[Fortes Marcelo]
>> but there are also benefits.  It's extremely hard to predict
>> performance of even simple software systems, and it is also
>> extremely hardware dependent.  For example, the cost of context
>> switches depends on the question if you have tagged TLBs and the
>> number of registers.

> And how can it be solved? By L4? i think not.

Actually yes.  An example of how the untagged TLBs problem can be
solved is given in [1].  Further, as the trend to go to 64 bit
addressing on IA32 continues, the "hack" of having a simple 4 level
page table scheme really starts to have an impact on TLB miss
performance.  This calls for larger TLBs (the AMD64 boxes have more
than 1K TLB entries), which again calls for having some way to avoid
flushing the complete TLB on context switches (e.g., the flush filter
from AMD).

We also design both the kernel and the architecture specific ABIs in a
wat so that as little work as possible need to be conducted by the
kernel when context switching during IPC.  For example, the register
contents of before and after invoking an IPC is defined so that the
kernel can discard the information within almost all registers.


[1] http://l4ka.org/publications/paper.php?docid=671

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