[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: Bochs 2.0.2 and L4ka

From: Laurent Gualdi
Subject: Re: Bochs 2.0.2 and L4ka
Date: Wed, 19 Mar 2003 04:03:58 +0100

Hi Farid,

> "The DE bit allows the Pentium+ to set breakpoints in I/O space using
> the breakpoint registers. The R/W coding 10b is used to indicate that
> the breakpoint is in I/O space on the Pentium+.  The 10b encoding was
> marked as 'invalid' for pre-Pentium CPUs."

I've also checked in the intel doc. 
If you set DE bit in CR4 to 1, access to DR4 and DR5 ( reserved debug 
register ) cause an invalid opcode exception (#UD).
if DE bit is set to 0, DR4 and DR5 are aliased to debug register DR6 and DR7.

I've checked bochs sources and it work like that.
It is done by the function "void BX_CPU_C::MOV_DdRd(bxInstruction_c *i)" in 

> hmmm, breakpoints handling may be somewhat hairy to handle.
> I withdraw my previous statement about implementing DE-bit fully.
> Perhaps forcing DE bit to 1 would be okay, as long as
> no kernel debugger in Hazelnut (or pistachio) needs it.

Do you know if bochs handle correctly breakpoints ?
If so, i don't think there is more stuff to do with this DE bit.



reply via email to

[Prev in Thread] Current Thread [Next in Thread]