Re: Partial generation of recipe and dependencies

[Paul Smith]

On Wed, 2012-06-20 at 23:08 -0700, Philip Guenther wrote:
> On Wed, Jun 20, 2012 at 3:20 PM, Andre Majorel <address@hidden> wrote:
> > On 2012-06-19 19:30 +0200, Andre Majorel wrote:
> >> define tgt
> >> .PHONY: $(1)
> >> $(1): destdir-unsafe
> >> endef
> >>
> >> $(eval $(call tgt, target1))
> >>       do something
> >>
> >> $(eval $(call tgt, target2))
> >>       do something else
> >>
> >> Unfortunately, the splicing of the two lines coming from $(tgt)
> >> and the "do something" line does not take place and Make bombs
> >> with
> >>
> >>   Makefile:#: *** commands commence before first target.  Stop.
> >>
> >> on the "do something" line. Any way to make it work ? Thanks in
> >> advance.
> >
> > No answers because it's a FAQ or because it's a tough one ?
> 
> -----
> define tgt
> $(eval .PHONY: $(value 1)
> $(value 1): destdir-unsafe)$(1):
> endef
> 
> $(call tgt, target1)
>         @echo something
> 
> $(call tgt, target2)
>         @echo something2
> -----

Ha!  That's very cute indeed Philip.  Nicely done.

For Andre: the reason this doesn't work is the same reason that an
"include" containing a target setup cannot be followed by the recipe for
that target after the include; this won't work:

        include target.mk
                @echo this is the recipe

For both include and $(eval ...) the makefile that is included or eval'd
is always parsed by make as if it were a self-contained makefile, and
the end-of-file (or end-of-string) markers will be interpreted by make
as ending any target that is currently being parsed.