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Re: Issues with compiling dependent objects
From: |
Philip Guenther |
Subject: |
Re: Issues with compiling dependent objects |
Date: |
Fri, 30 May 2008 17:57:22 -0600 |
[Whoops, forgot to cc the list]
On Fri, May 30, 2008 at 5:29 PM, Garrett Cooper <address@hidden> wrote:
> On Wed, May 28, 2008 at 10:19 PM, Garrett Cooper <address@hidden> wrote:
>>
>> On Wed, May 28, 2008 at 4:25 PM, Philip Guenther <address@hidden>
>> wrote:
>>> On Wed, May 28, 2008 at 12:59 PM, Garrett Cooper <address@hidden>
>>> wrote:
...
>>> > How do I disable -r action?
>>>
>>> Either
>>> 1) don't set it to begin with (why are they?), or
>>> 2) explicitly include the rules you need.
...
> Another question along these lines... would filtering MAKEFLAGS in
> the makefile yield the same type of logic that I'm looking for?
The -r option takes effect before the makefile is parsed; nothing in
the makefile can prevent it from working or, contrawise, force it when
it wasn't there.
Hmm, I suppose you could detect that it was used and force a
reinvocation without it. Say, if your real rules are in the file
"Makefile", then you could put something like the following in the
file "GNUmakefile":
ifneq ($(findstring r,${MAKEFLAGS}),)
# XXX what about long options that contain an 'r'?
$(warning -r option used; reinvoking to turn it off)
MAKEFLAGS = $(subst r,,${MAKEFLAGS})
ifeq (${MAKECMDGOALS},)
target = fakefake
else
target = $(firstword ${MAKECMDGOALS})
endif
${target}:
@${MAKE} ${MAKECMDGOALS}
.PHONY: ${target} ${MAKECMDGOALS}
fakefake2 $(wordlist 2,$(words ${MAKECMDGOALS}),${MAKECMDGOALS}):
@: nothing
else
include Makefile
endif
...but the $(findstring) and $(subst) aren't really right, and fixing
them to be correct in the face of options like
--warn-undefined-variables (notice the 'r') or command-line variable
assignments that contain an 'r' would be a pain. Perhaps someone else
has a brilliant idea for doing that...
...or maybe there should be an option to restore the normal behavior,
similar to how -S cancels -k.
Philip Guenther