again, i have a given list of C source files, each of which has the
following structure:
blah.c:
#ifdef OBJ_fred
... what will be compiled to generate fred.o ...
#endif
#ifdef OBJ_astro
... what will be compiled to generate astro.o
#endif
... and so on ...
there is no clear pattern between the name of the source file and
the names of the object files that it can generate. each source file
will be compiled several times, defining a different preprocessor
directive each time to generate the corresponding object file. so
far, so good?
for a file like the one above, the generated makefile rule would
resemble:
fred.o astro.o: blah.c
... funky rule to build each object file ...
now, given the list of source files, for each source file, i could
easily generate the list of corresponding object files using "grep"
so, for a given ${SRCFILE}, i would have:
OBJFILES := $(addsuffix .o,
$(shell grep -h "^\#ifdef OBJ_" ${SRCFILE} | \
sed -e "s/^\#ifdef OBJ_//"))