Re: undocumented make features

[Paul D. Smith]

%% Boris Kolpackov <address@hidden> writes:

  bk> I have a few questions about undocumented/surprising behavior of 
  bk> gnu make.

Wow, this message got _REALLY_ lost in my inbox.  Sorry :-(.

  bk> define set
  bk> $(eval $1:=$2)
  bk> endef

  bk> $(call set,foo,bar)

  bk> all:; @echo $(foo)

  bk> It works fine with make 3.80 even though manual doesn't say it's legal
  bk> to use $(call ) like this.

Why wouldn't it be?  The expansion of $(eval ...) is always the empty
string, so the result of expanding the call function is the empty
string... and the empty string can't be a syntax error!

Just like this:

    FOO =

    $(FOO)

is perfectly legal.

  bk> -------------
  bk> # Included.mk
  bk> foo := bar
  bk> -------------

  bk> -------------
  bk> define include
  bk> $(eval include $1)
  bk> endef
  bk> $(call include,Included.mk)
  bk> all:; @echo $(foo)
  bk> -------------

  bk> Even though 'include' is a keyword.

That doesn't matter.  The syntax for makefiles won't allow the keyword
"include" and a variable named "include" to ever be confused for each
other.

If the line has the syntax of a variable assignment then it's a
variable, even if it would otherwise be considered a keyword.

-- 
-------------------------------------------------------------------------------
 Paul D. Smith <address@hidden>          Find some GNU make tips at:
 http://www.gnu.org                      http://make.paulandlesley.org
 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist