makefile question

[Liang]

Hi,

I'm facing headache when I try to write a gnu makefile for a project. Due to
the existing source directory structure of the project, the makefiles have
to be saved away from the source files, and the interim files and output
files need to be saved in a sub-dir of the makefile. The project source file
directory structure looks like:

/pjt_root/
    /part1/
        /file1.c
        /file1.h
    /part2/
        /file2.c
        /file2.h
    /config/
        /makefile
        /debug/
            /file1.o
            /file2.o
            /a.out
        /release/
            /file1.o
            /file2.o
            /a.out

If the target is for debug purpose, all .o and .out will be in 'debug'
purpose. The same rule applies to 'release'.

The makefile looks like:

SRC= part1/file1.c part2/file2.c
$OBJECTS:= $(foreach src, $(SRC),  $(basename $(notdir $(src))).o)

ALL_Debug: debug/a.out
OBJECTS_Debug:=$(foreach obj, $(OBJECTS), debug/$(obj))
debug/a.out: $(OBJECTS_Debug)
    $(CC) $(CFLAGS) -o $@ $<

%.o:%.c
    $(CC) $(CFLAGS) -c $<

But the problem comes. 'make' does NOT know how to make debug/file1.o
debug/file2.o.

Do I need to change the suffix rule as "$(target_folder)/%.o:%.c", and
specify VPATH= $(foreach src, $(SRC), $(dir $(src))) for c files at the same
time? But this approach not only looks awkward, but also error-prone. And
the rule doesn't work well.

May u kindly point out a better solution for this scenario? Thanks.

Regards,
Liang