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[Guile-commits] 14/58: Recognize RISC-V compilation targets.

From: Andy Wingo
Subject: [Guile-commits] 14/58: Recognize RISC-V compilation targets.
Date: Tue, 7 Aug 2018 06:58:30 -0400 (EDT)

wingo pushed a commit to branch lightning
in repository guile.

commit 2662cafd6a22768b5d92b82038815e9f5385d017
Author: Shea Levy <address@hidden>
Date:   Sun Feb 25 20:34:39 2018 -0500

    Recognize RISC-V compilation targets.
    * module/system/base/target.scm (cpu-endianness): Add case for "riscv" 
    Signed-off-by: Shea Levy <address@hidden>
    Signed-off-by: Mark H Weaver <address@hidden>
 module/system/base/target.scm | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/module/system/base/target.scm b/module/system/base/target.scm
index 95ab8d8..93616f4 100644
--- a/module/system/base/target.scm
+++ b/module/system/base/target.scm
@@ -86,6 +86,8 @@
              (endianness big))
             ((string=? "aarch64" cpu)
              (endianness little))
+            ((string-match "riscv[1-9][0-9]*" cpu)
+             (endianness little))
              (error "unknown CPU endianness" cpu)))))

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