[Guile-commits] 207/437: Correct race condition if register is written m

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[Guile-commits] 207/437: Correct race condition if register is written m

From:	Andy Wingo
Subject:	[Guile-commits] 207/437: Correct race condition if register is written more than once
Date:	Mon, 2 Jul 2018 05:14:21 -0400 (EDT)

wingo pushed a commit to branch lightning
in repository guile.

commit b663d29beaac309b29f1a93c9921c73b052de8ed
Author: pcpa <address@hidden>
Date:   Fri Apr 26 21:26:00 2013 -0300

    Correct race condition if register is written more than once
    
        * lib/jit_ia64-cpu.c, lib/jit_ia64-fpu.c: Correct code to
        also insert a stop to break an instruction group if a
        register is written more than once in the same group.
        This may happen if a register is argument and result of
        some lightning call (not a real instruction). The most
        common case should be code in the pattern:
                movl rn=largenum
                ...
                mov rn=smallnum
        where "rn" would end up holding "largenum".
        But the problem possibly could happen in other circumstances.
---
 ChangeLog          | 14 ++++++++++++++
 lib/jit_ia64-cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++
 lib/jit_ia64-fpu.c | 10 ++++++++++
 3 files changed, 64 insertions(+)

diff --git a/ChangeLog b/ChangeLog
index 18f6440..7468631 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,19 @@
 2013-04-26 Paulo Andrade <address@hidden>
 
+       * lib/jit_ia64-cpu.c, lib/jit_ia64-fpu.c: Correct code to
+       also insert a stop to break an instruction group if a
+       register is written more than once in the same group.
+       This may happen if a register is argument and result of
+       some lightning call (not a real instruction). The most
+       common case should be code in the pattern:
+               movl rn=largenum
+               ...
+               mov rn=smallnum
+       where "rn" would end up holding "largenum".
+       But the problem possibly could happen in other circumstances.
+
+2013-04-26 Paulo Andrade <address@hidden>
+
        * include/lightning/jit_ia64.h, lib/jit_ia64-cpu.c,
        lib/jit_ia64-fpu.c, lib/jit_ia64.c:
          Relocate JIT_Rn registers to the local registers, as, like
diff --git a/lib/jit_ia64-cpu.c b/lib/jit_ia64-cpu.c
index 009b350..dc4f4f1 100644
--- a/lib/jit_ia64-cpu.c
+++ b/lib/jit_ia64-cpu.c
@@ -2031,6 +2031,7 @@ _A1(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((8L<<37)|(x4<<29)|(x2<<27)|(r3<<20)|(r2<<13)|(r1<<6)|_p, INST_A);
     SETREG(r1);
 }
@@ -2047,6 +2048,7 @@ _A3(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7f));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((8L<<37)|(((im>>7)&1L)<<36)|(x4<<29)|(x2<<27)|
         (r3<<20)|((im&0x7fL)<<13)|(r1<<6)|_p, INST_A);
     SETREG(r1);
@@ -2063,6 +2065,7 @@ _A4(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1  & ~0x7f));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((8L<<37)|(((im>>13)&1L)<<36)|(x2<<34)|(((im>>7)&0x3fL)<<27)|
         (r3<<20)|((im&0x7fL)<<13)|(r1<<6)|_p, INST_A);
     SETREG(r1);
@@ -2078,6 +2081,7 @@ _A5(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1  & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((9L<<37)|(((im>>7)&0x7fffL)<<22)|(r3<<20)|
         ((im&0x7fL)<<13)|(r1<<6)|_p, INST_A);
     SETREG(r1);
@@ -2169,6 +2173,7 @@ _A9(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((8L<<37)|(za<<36)|(1L<<34)|(zb<<33)|(x4<<29)|(x2<<27)|
         (r3<<20)|(r2<<13)|(r1<<6)|_p, INST_A);
     SETREG(r1);
@@ -2186,6 +2191,7 @@ _I1(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((7L<<37)|(1L<<33)|(ct<<30)|(x2<<28)|
         (r3<<20)|(r2<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2207,6 +2213,7 @@ _I2(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((7L<<37)|(za<<36)|(xa<<34)|(zb<<33)|(xc<<30)|
         (xb<<28)|(r3<<20)|(r2<<13)|(r1<<6), INST_I);
     SETREG(r1);
@@ -2222,6 +2229,7 @@ _I3(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG1(r2);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((7L<<37)|(3L<<34)|(2L<<30)|(2L<<28)|
         (mb<<20)|(r2<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2237,6 +2245,7 @@ _I4(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG1(r2);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((7L<<37)|(3L<<34)|(1L<<33)|(2L<<30)|
         (2L<<28)|(mh<<20)|(r2<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2256,6 +2265,7 @@ _I5(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((7L<<37)|(za<<36)|(zb<<33)|(x2<<28)|
         (r3<<20)|(r2<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2275,6 +2285,7 @@ _I6(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((7L<<37)|(za<<36)|(1L<<34)|(zb<<33)|
         (x2<<28)|(r3<<20)|(ct<<14)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2292,6 +2303,7 @@ _I7(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((7L<<37)|(za<<36)|(zb<<33)|(1L<<30)|
         (r3<<20)|(r2<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2309,6 +2321,7 @@ _I8(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG1(r2);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((7L<<37)|(za<<36)|(3L<<34)|(zb<<33)|(1L<<30)|(1L<<28)|
         (im<<20)|(r2<<13)|(r1<<6), INST_I);
     SETREG(r1);
@@ -2324,6 +2337,7 @@ _I9(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((7L<<37)|(1L<<34)|(1L<<34)|(1L<<33)|
         (x2<<30)|(1L<<28)|(r3<<20)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2340,6 +2354,7 @@ _I10(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((5L<<37)|(3L<<34)|(ct<<27)|(r3<<20)|(r2<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
 }
@@ -2357,6 +2372,7 @@ _I11(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1  & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((5L<<37)|(1L<<34)|(len<<27)|(r3<<20)|
         (pos<<14)|(y<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2373,6 +2389,7 @@ _I12(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1  & ~0x7fL));
     TSTREG1(r2);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((5L<<37)|(1L<<34)|(1L<<33)|(len<<27)|
         (pos<<20)|(r2<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2388,6 +2405,7 @@ _I13(jit_state_t *_jit, jit_word_t _p,
     assert(!(im  & ~0x7fL));
     assert(!(r1  & ~0x7fL));
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((5L<<37)|(((im>>7)&1L)<<36)|(1L<<34)|(1L<<33)|(len<<27)|
         (1L<<26)|(pos<<20)|((im&0x7fL)<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2405,6 +2423,7 @@ _I14(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1  & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((5L<<37)|(s<<36)|(3L<<34)|(1L<<33)|
         (len<<27)|(r3<<20)|(pos<<14)|(r1<<6)|_p, INST_I);
     SETREG(r1);
@@ -2423,6 +2442,7 @@ _I15(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1  & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((4L<<37)|(pos<<31)|(len<<27)|(r3<<20)|(r2<<13)|(r1<<6)|_p, INST_I);
     SETREG(r1);
 }
@@ -2567,6 +2587,7 @@ _I25(jit_state_t *_jit, jit_word_t _p,
     assert(!(x6 & ~0x3fL));
     assert(!(r1 & ~0x7fL));
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((x6<<27)|(r1<<6)|_p, INST_I);
     SETREG(r1);
 }
@@ -2602,6 +2623,7 @@ _I28(jit_state_t *_jit, jit_word_t _p,
     assert(!(ar & ~0x7fL));
     assert(!(r1 & ~0x7fL));
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((0x32L<<27)|(ar<<20)|(r1<<6)|_p, INST_I);
     SETREG(r1);
 }
@@ -2616,6 +2638,7 @@ _I29(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((x6<<27)|(r3<<20)|(r1<<6)|_p, INST_I);
     SETREG(r1);
 }
@@ -2653,6 +2676,7 @@ _M1(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((4L<<37)|(x6<<30)|(ht<<28)|(x<<27)|(r3<<20)|(r1<<6)|_p, INST_M);
     SETREG(r1);
 }
@@ -2669,6 +2693,7 @@ _M2(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((4L<<37)|(1L<<36)|(x6<<30)|(ht<<28)|
         (r3<<20)|(r2<<13)|(r1<<6)|_p, INST_M);
     SETREG(r1);
@@ -2688,6 +2713,7 @@ _M3(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 &  ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((5L<<37)|(((im>>8)&1L)<<36)|(x6<<30)|(ht<<28)|
         (((im>>7)&1L)<<27)|(r3<<20)|((im&0x7fL)<<13)|(r1<<6)|_p, cc);
     SETREG(r1);
@@ -2783,6 +2809,7 @@ _M16(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((4L<<37)|(x6<<30)|(ht<<28)|(1L<<27)|
         (r3<<20)|(r2<<13)|(r1<<6)|_p, INST_M);
     SETREG(r1);
@@ -2800,6 +2827,7 @@ _M17(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((4L<<37)|(x6<<30)|(ht<<28)|(1L<<27)|
         (r3<<20)|(im<<13)|(r1<<6)|_p, INST_M);
     SETREG(r1);
@@ -2831,6 +2859,10 @@ _M22x(jit_state_t *_jit, jit_word_t _p,
     assert(!(im & ~0x1fffffL));
     assert(!(r1 &     ~0x7fL));
     TSTPRED(_p);
+    if (x3 < 6)
+       TSTREG1(r1);
+    else
+       TSTFREG1(r1);
     inst((((im>>20)&1L)<<36)|(x3<<33)|((im&0xffffL)<<13)|(r1<<6)|_p, INST_M);
     if (x3 < 6)
        SETREG(r1);
@@ -2908,6 +2940,7 @@ _M31(jit_state_t *_jit, jit_word_t _p,
     assert(!(ar  & ~0x7L));
     assert(!(r1 & ~0x7fL));
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((1L<<37)|(0x22L<<27)|(ar<<20)|(r1<<6)|_p, INST_M);
     SETREG(r1);
 }
@@ -2932,6 +2965,7 @@ _M33(jit_state_t *_jit, jit_word_t _p,
     assert(!(cr  & ~0x7L));
     assert(!(r1 & ~0x7fL));
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((1L<<37)|(0x24L<<27)|(cr<<20)|(r1<<6)|_p, INST_M);
     SETREG(r1);
 }
@@ -2969,6 +3003,7 @@ _M36(jit_state_t *_jit, jit_word_t _p,
     assert(!(x6 & ~0x3fL));
     assert(!(r1 & ~0x7fL));
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((1L<<37)|(x6<<27)|(r1<<6)|_p, INST_M);
     SETREG(r1);
 }
@@ -2994,6 +3029,7 @@ _M38(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 &  ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((1L<<37)|(x6<<27)|(r3<<20)|(r2<<13)|(r1<<6)|_p, INST_M);
     SETREG(r1);
 }
@@ -3009,6 +3045,7 @@ _M39(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 &  ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((1L<<37)|(x6<<27)|(r3<<20)|(im<<13)|(r1<<6)|_p, INST_M);
     SETREG(r1);
 }
@@ -3060,6 +3097,7 @@ _M43(jit_state_t *_jit, jit_word_t _p,
     assert(!(r3 &  ~0x7fL));
     assert(!(r1 &  ~0x7fL));
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((1L<<37)|(x6<<27)|(r3<<20)|(r1<<6)|_p, INST_M);
     SETREG(r1);
 }
@@ -3099,6 +3137,7 @@ _M46(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    if (r1)    TSTREG1(r1);
     inst((1L<<37)|(x6<<27)|(r3<<20)|(r1<<6)|_p, INST_M);
     if (r1)    SETREG(r1);
 }
@@ -3255,6 +3294,7 @@ _X2(jit_state_t *_jit, jit_word_t _p,
     i7  =  im        &          0x7fL;
     inst(i41, INST_L);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((6L<<37)|(i1<<36)|(i9<<27)|(i5<<22)|
         (ic<<21)|(i7<<13)|(r1<<6)|_p, INST_X);
     SETREG(r1);
diff --git a/lib/jit_ia64-fpu.c b/lib/jit_ia64-fpu.c
index ee58cac..1c24df8 100644
--- a/lib/jit_ia64-fpu.c
+++ b/lib/jit_ia64-fpu.c
@@ -704,6 +704,7 @@ _M7(jit_state_t *_jit, jit_word_t _p,
     assert(!(f1 & ~0x7fL));
     TSTREG2(r2, r3);
     TSTPRED(_p);
+    TSTFREG1(f1);
     inst((6L<<37)|(1L<<36)|(x6<<30)|(ht<<28)|
         (r3<<20)|(r2<<13)|(f1<<6)|_p, INST_M);
     SETFREG(f1);
@@ -722,6 +723,7 @@ _M8(jit_state_t *_jit, jit_word_t _p,
     assert(!(f1 &  ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTFREG1(f1);
     inst((7L<<37)|(((im>>8)&1L)<<36)|(x6<<30)|(ht<<28)|
         (((im>>8)&1L)<<27)|(r3<<20)|((im&0x7fLL)<<13)|(f1<<6)|_p, INST_M);
     SETFREG(f1);
@@ -739,6 +741,7 @@ _M9(jit_state_t *_jit, jit_word_t _p,
     assert(!(f1 & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTFREG1(f1);
     inst((6L<<37)|(x6<<30)|(ht<<28)|(r3<<20)|(f1<<6)|_p, INST_M);
     SETFREG(f1);
 }
@@ -773,6 +776,7 @@ _M11(jit_state_t *_jit, jit_word_t _p,
     assert(!(f1 & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTFREG2(f1, f2);
     inst((6L<<37)|(x6<<30)|(ht<<28)|(1L<<27)|
         (r3<<20)|(f2<<13)|(f1<<6)|_p, INST_M);
     SETFREG(f1);
@@ -791,6 +795,7 @@ _M12(jit_state_t *_jit, jit_word_t _p,
     assert(!(f1 & ~0x7fL));
     TSTREG1(r3);
     TSTPRED(_p);
+    TSTFREG2(f1, f2);
     inst((6L<<37)|(1L<<36)|(x6<<30)|(ht<<28)|
         (1L<<27)|(r3<<20)|(f2<<13)|(f1<<6)|_p, INST_M);
     SETFREG(f1);
@@ -808,6 +813,7 @@ _M18(jit_state_t *_jit, jit_word_t _p,
     assert(!(f1 & ~0x7fL));
     TSTREG1(r2);
     TSTPRED(_p);
+    TSTFREG1(f1);
     inst((6L<<37)|(x6<<30)|(1L<<27)|(r2<<13)|(f1<<6)|_p, INST_M);
     SETFREG(f1);
 }
@@ -822,6 +828,7 @@ _M19(jit_state_t *_jit, jit_word_t _p,
     assert(!(r1 & ~0x7fL));
     TSTFREG1(f2);
     TSTPRED(_p);
+    TSTREG1(r1);
     inst((4L<<37)|(x6<<30)|(1L<<27)|(f2<<13)|(r1<<6)|_p, INST_M);
     SETREG(r1);
 }
@@ -841,6 +848,7 @@ F1_(jit_state_t *_jit, jit_word_t _p,
     assert(!(f1 & ~0x7fL));
     TSTFREG3(f2, f3, f4);
     TSTPRED(_p);
+    TSTFREG1(f1);
     inst((op<<37)|(x<<36)|(sf<<34)|(f4<<27)|
         (f3<<20)|(f2<<13)|(f1<<6)|_p, INST_F);
     SETFREG(f1);
@@ -905,6 +913,7 @@ F6x_(jit_state_t *_jit, jit_word_t _p,
     assert(!(f1 & ~0x7fL));
     TSTFREG2(f2, f3);
     TSTPRED(_p);
+    TSTFREG1(f1);
     inst((op<<37)|(q<<36)|(sf<<34)|(1L<<33)|
         (p2<<27)|(f3<<20)|(f2<<13)|(f1<<6)|_p, INST_F);
     SETFREG(f1);
@@ -926,6 +935,7 @@ F8_(jit_state_t *_jit, jit_word_t _p,
     assert(!(f1 & ~0x7fL));
     TSTFREG2(f2, f3);
     TSTPRED(_p);
+    TSTFREG1(f1);
     inst((op<<37)|(sf<<34)|(x6<<27)|(f3<<20)|(f2<<13)|(f1<<6)|_p, INST_F);
     SETFREG(f1);
 }

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- [Guile-commits] 321/437: x86: Correct not released temporary register, Andy Wingo, 2018/07/02
- [Guile-commits] 315/437: Add string representation of IR codes to -sz.c files, Andy Wingo, 2018/07/02
- [Guile-commits] 402/437: Correct wrong check for argument of value 2 in check/fib.tst., Andy Wingo, 2018/07/02
- [Guile-commits] 374/437: Add initial support to implement vararg jit functions, Andy Wingo, 2018/07/02
- [Guile-commits] 171/437: Add the new ccall test case to test interleaved C and jit function calls, Andy Wingo, 2018/07/02
- [Guile-commits] 51/437: switch to GPLv3, Andy Wingo, 2018/07/02
- [Guile-commits] 160/437: Correct bogus logic caused by wrong optimizations., Andy Wingo, 2018/07/02
- [Guile-commits] 05/437: use autoheader like every other package in this world, Andy Wingo, 2018/07/02
- [Guile-commits] 341/437: Add missing float rsbi strings, Andy Wingo, 2018/07/02
- [Guile-commits] 296/437: ALPHA: Implement lightning Alpha port., Andy Wingo, 2018/07/02
- [Guile-commits] 207/437: Correct race condition if register is written more than once, Andy Wingo <=
- [Guile-commits] 394/437: Move multiply defined macro to a single header file., Andy Wingo, 2018/07/02
- [Guile-commits] 366/437: Correct inconsistency with jit_regno_patch, Andy Wingo, 2018/07/02
- [Guile-commits] 421/437: Remove documentation from embedded GNU lightning, Andy Wingo, 2018/07/02
- [Guile-commits] 195/437: Minor updates when testing on a prototype, quadcore Loongson mips., Andy Wingo, 2018/07/02
- [Guile-commits] 332/437: Add test case to check possible issues with 2 contexts, Andy Wingo, 2018/07/02
- [Guile-commits] 189/437: Pass all but the (not yet implemented) qmul and qdiv tests in sparc, Andy Wingo, 2018/07/02
- [Guile-commits] 217/437: Adjust lightning to work on ppc AIX., Andy Wingo, 2018/07/02
- [Guile-commits] 223/437: Build and pass all tests on big endian Irix mips using the n32 abi., Andy Wingo, 2018/07/02
- [Guile-commits] 205/437: Properly split instruction groups for predicate registers., Andy Wingo, 2018/07/02
- [Guile-commits] 391/437: aarch64: Correct va_list offsets and double load., Andy Wingo, 2018/07/02

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