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[Guile-commits] 119/437: Correct branches and several ALU operations wit
From: |
Andy Wingo |
Subject: |
[Guile-commits] 119/437: Correct branches and several ALU operations with 64 immediates |
Date: |
Mon, 2 Jul 2018 05:13:57 -0400 (EDT) |
wingo pushed a commit to branch lightning
in repository guile.
commit d4a2a1ba0742c8c0c98a404c0e92cce45b12b5db
Author: Paulo Cesar Pereira de Andrade <address@hidden>
Date: Thu Aug 26 20:01:11 2010 -0300
Correct branches and several ALU operations with 64 immediates
jit_bra_l had the logic reversed, and correcting that also corrected
jit_b{lt,le,eq,ge,gt,ne}i_l.
TESTQir and _ALUQir were not properly working with 64 bit immediates,
that require using a temporary register (JIT_REXTMP) as there are no
related opcodes for 64 bit immediates. This corrected jit_bm{s,c}i_l and
jit_bo{add,sub}i_l.
Now, the tests in
http://code.google.com/p/exl/source/browse/trunk/check/lightning/branch.tst
pass.
---
lightning/i386/asm-64.h | 12 +++++++++---
lightning/i386/asm.h | 12 +++++++++---
lightning/i386/core-64.h | 6 +++---
3 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/lightning/i386/asm-64.h b/lightning/i386/asm-64.h
index deaf1a8..9b882f9 100644
--- a/lightning/i386/asm-64.h
+++ b/lightning/i386/asm-64.h
@@ -297,9 +297,15 @@
#define TESTQrr(RS, RD) (_REXQrr(RS, RD),
_O_Mrm (0x85 ,_b11,_r8(RS),_r8(RD)
))
#define TESTQrm(RS, MD, MB, MI, MS) (_REXQrm(RS, MB, MI), _O_r_X
(0x85 ,_r8(RS) ,MD,MB,MI,MS ))
-#define TESTQir(IM, RD) (!_s8P(IM) && (RD) == _RAX ? \
- (_REXQrr(0, RD), _O_L
(0xa9 ,IM )) : \
- (_REXQrr(0, RD),
_O_Mrm_L (0xf7 ,_b11,_b000 ,_r8(RD) ,IM
)) )
+#define TESTQir(IM, RD)
\
+ /* Immediate fits in 32 bits? */ \
+ (_s32P((long)(IM)) \
+ /* Yes. Immediate does not fit in 8 bits and reg is %rax? */ \
+ ? (!_s8P(IM) && (RD) == _RAX \
+ ? (_REXQrr(0, RD), _O_L(0xa9, IM)) \
+ : (_REXQrr(0, RD), _O_Mrm_L(0xf7, _b11, _b000, _r8(RD), IM))) \
+ /* No. Need immediate in a register */ \
+ : (MOVQir(IM, JIT_REXTMP), TESTQrr(JIT_REXTMP, RD)))
#define TESTQim(IM, MD, MB, MI, MS) (_REXQrm(0, MB, MI),
_O_r_X_L (0xf7 ,_b000 ,MD,MB,MI,MS ,IM
))
#define CMPXCHGQrr(RS, RD) (_REXQrr(RS, RD), _OO_Mrm
(0x0fb1 ,_b11,_r8(RS),_r8(RD) ))
diff --git a/lightning/i386/asm.h b/lightning/i386/asm.h
index 29f3ab1..8412ce7 100644
--- a/lightning/i386/asm.h
+++ b/lightning/i386/asm.h
@@ -337,9 +337,15 @@ enum {
#define _ALUQrr(OP, RS, RD) (_REXQrr(RS, RD), _O_Mrm
(((OP) << 3) + 1,_b11,_r8(RS),_r8(RD) ))
#define _ALUQmr(OP, MD, MB, MI, MS, RD) (_REXQmr(MB, MI, RD),
_O_r_X (((OP) << 3) + 3 ,_r8(RD) ,MD,MB,MI,MS
))
#define _ALUQrm(OP, RS, MD, MB, MI, MS) (_REXQrm(RS, MB, MI),
_O_r_X (((OP) << 3) + 1 ,_r8(RS) ,MD,MB,MI,MS
))
-#define _ALUQir(OP, IM, RD) (!_s8P(IM) && (RD) == _RAX ? \
- (_REXQrr(0, RD), _O_L
(((OP) << 3) + 5 ,IM )) : \
- (_REXQrr(0, RD),
_Os_Mrm_sL (0x81 ,_b11,OP ,_r8(RD) ,IM
)) )
+#define _ALUQir(OP, IM, RD) \
+ /* Immediate fits in 32 bits? */ \
+ (_s32P((long)(IM)) \
+ /* Yes. Immediate does not fit in 8 bits and reg is %rax? */ \
+ ? (!_s8P(IM) && (RD) == _RAX \
+ ? (_REXQrr(0, RD), _O_L(((OP) << 3) + 5, IM)) \
+ : (_REXQrr(0, RD), _Os_Mrm_sL(0x81, _b11, OP, _r8(RD), IM))) \
+ /* No. Need immediate in a register */ \
+ : (MOVQir(IM, JIT_REXTMP), _ALUQrr(OP, JIT_REXTMP, RD)))
#define _ALUQim(OP, IM, MD, MB, MI, MS) (_REXQrm(0, MB, MI),
_Os_r_X_sL (0x81 ,OP ,MD,MB,MI,MS ,IM
))
#define ADCBrr(RS, RD) _ALUBrr(X86_ADC, RS, RD)
diff --git a/lightning/i386/core-64.h b/lightning/i386/core-64.h
index 48a8996..1214850 100644
--- a/lightning/i386/core-64.h
+++ b/lightning/i386/core-64.h
@@ -98,7 +98,7 @@ struct jit_local_state {
#define jit_bra_l(rs, is, op) (_s32P((long)(is)) \
? _jit_bra_l(rs, is, op) \
- : (MOVQir(is, JIT_REXTMP),
jit_bra_qr(JIT_REXTMP, rs, op)))
+ : (MOVQir(is, JIT_REXTMP), jit_bra_qr(rs,
JIT_REXTMP, op)))
/* When CMP with 0 can be replaced with TEST */
#define jit_bra_l0(rs, is, op, op0) \
@@ -307,8 +307,8 @@ static int jit_arg_reg_order[] = { _EDI, _ESI, _EDX, _ECX,
_R8D, _R9D };
#define jit_blei_ul(label, rs, is) jit_bra_l0((rs), (is), JBEm(label),
JEm(label) )
#define jit_bgti_ul(label, rs, is) jit_bra_l0((rs), (is), JAm(label),
JNEm(label) )
#define jit_bgei_ul(label, rs, is) jit_bra_l ((rs), (is), JAEm(label)
)
-#define jit_bmsi_l(label, rs, is) jit_bmsi_i(label, rs, is)
-#define jit_bmci_l(label, rs, is) jit_bmci_i(label, rs, is)
+#define jit_bmsi_l(label, rs, is) (jit_reduceQ(TEST, (is), (rs)),
JNZm(label), _jit.x.pc)
+#define jit_bmci_l(label, rs, is) (jit_reduceQ(TEST, (is), (rs)),
JZm(label), _jit.x.pc)
#define jit_pushr_l(rs) jit_pushr_i(rs)
#define jit_popr_l(rs) jit_popr_i(rs)
- [Guile-commits] 153/437: Make it clear stdarg like abstraction is not supported., (continued)
- [Guile-commits] 153/437: Make it clear stdarg like abstraction is not supported., Andy Wingo, 2018/07/02
- [Guile-commits] 76/437: fix several load/store patterns for x86-64., Andy Wingo, 2018/07/02
- [Guile-commits] 81/437: fix stack alignment for Apple 32-bit ABI, Andy Wingo, 2018/07/02
- [Guile-commits] 98/437: always set and replace lightning_frag, Andy Wingo, 2018/07/02
- [Guile-commits] 166/437: Correct extra regressions found by the call.tst test case., Andy Wingo, 2018/07/02
- [Guile-commits] 165/437: Add simple test case to test argument and return values., Andy Wingo, 2018/07/02
- [Guile-commits] 158/437: Add new test case to check stack integrity on complex stack frames., Andy Wingo, 2018/07/02
- [Guile-commits] 150/437: Add jit_ellipis and remove jit_prepare argument., Andy Wingo, 2018/07/02
- [Guile-commits] 108/437: fix x86_64 jit_bner_{f,d}, Andy Wingo, 2018/07/02
- [Guile-commits] 122/437: Correct ALU add and sub operations with 64 bit immediate operands., Andy Wingo, 2018/07/02
- [Guile-commits] 119/437: Correct branches and several ALU operations with 64 immediates,
Andy Wingo <=
- [Guile-commits] 135/437: Correct implementation problems on ix86., Andy Wingo, 2018/07/02
- [Guile-commits] 169/437: Correct wrong and confusing reverse float comparison logic, Andy Wingo, 2018/07/02
- [Guile-commits] 139/437: Implement sqrt codes in mips., Andy Wingo, 2018/07/02
- [Guile-commits] 134/437: Correct make distcheck., Andy Wingo, 2018/07/02
- [Guile-commits] 156/437: Simplify listing of test cases with alternate jit generation options, Andy Wingo, 2018/07/02
- [Guile-commits] 157/437: Add two extra test cases for float operations., Andy Wingo, 2018/07/02
- [Guile-commits] 161/437: Add new register clobber detection test case., Andy Wingo, 2018/07/02
- [Guile-commits] 164/437: Add new carry test case., Andy Wingo, 2018/07/02
- [Guile-commits] 138/437: Correct mips backend implementation to pass initial tests., Andy Wingo, 2018/07/02
- [Guile-commits] 163/437: Add missing jit_htonr to ppc backend., Andy Wingo, 2018/07/02