#grep -r FMAP__COREBOOT_SIZE
src/soc/intel/baytrail/romstage/cache_as_ram.inc:#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE)
src/lib/cbfs.c: size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE;
build/fmap_config.h:#define ___FMAP__COREBOOT_SIZE 0xc1d800
#cat src/mainboard/intel/leafhill/leafhill.16384.fmd
FLASH 16M {
address@hidden 0x1000
address@hidden 0x2ff000
address@hidden 0x800
COREBOOT(CBFS)@0x300800 0xc1d800
address@hidden 0x21000 {
address@hidden 0x10000
address@hidden 0x10000
address@hidden 0x1000
}
address@hidden 0x40000
address@hidden 0x7f000
address@hidden 0x1000
}