Fixes and cleanup of ARM cache maintenance code

[Leif Lindholm]

The current version of ARM cache maintenance code contains a few bugs,
preventing GRUB from running properly on my hardware platforms.

Main issues are that clean_dcache_range/invalidate_icache_range use the
addresses of grub_arch_cache_dlinesz/grub_arch_cache_ilinesz rather
than the values read in probe_caches().

ChangeLog:
2013-09-10  Leif Lindholm  <address@hidden>
        * kern/arm/cache.S: correct access to ilinesz/dlinesz variables
                            clean up stack manipulation (sync_caches_armv*)

=== modified file 'grub-core/kern/arm/cache.S'
--- grub-core/kern/arm/cache.S  2013-05-16 23:33:22 +0000
+++ grub-core/kern/arm/cache.S  2013-09-10 16:30:20 +0000
@@ -37,6 +37,7 @@
 clean_dcache_range:
        @ Clean data cache for range to point-of-unification
        ldr     r2, =EXT_C(grub_arch_cache_dlinesz)
+       ldr     r2, [r2]
        sub     r3, r2, #1              @ align "beg" to start of line
        mvn     r3, r3
        and     r0, r0, r3
@@ -57,6 +58,7 @@
 invalidate_icache_range:
        @ Invalidate instruction cache for range to point-of-unification
        ldr     r2, =EXT_C(grub_arch_cache_ilinesz)
+       ldr     r2, [r2]
        sub     r3, r2, #1              @ align "beg" to start of line
        mvn     r3, r3
        and     r0, r0, r3
@@ -77,14 +79,13 @@
 #else
 FUNCTION(grub_arch_sync_caches_armv7)
 #endif
+       DSB
        add     r1, r0, r1
-       DSB
-       push    {r0-r1, r4-r6, lr}
-       ldrdeq  r0, r1, [sp]
+       push    {r0-r2, lr}
        bl      clean_dcache_range
        pop     {r0, r1}
        bl      invalidate_icache_range
-       pop     {r4-r6, pc}
+       pop     {r2, pc}
 
 #ifdef ARMV6
 FUNCTION(grub_arm_disable_caches_mmu_armv6)