|Subject:||Re: Timing via serial port|
|Date:||Wed, 30 Sep 2020 14:19:34 +0200|
I've measured the delay between the 1PPS signal and the TX uart output on the NEO-M9N board with a logic analyzer. I would need to find the or re-measure the data for you tonight.
Front edge of the UART frame is the most precise. Rear edge depends too much on the length of the message.
As I recall, the latency from the PPS to the front edge increases(!) with increasing update rate. I did not check for the variation between the 1PPS and the start of the UART message.
From: "O'Connor, Daniel"
Sent: Wed Sep 30 14:08:21 GMT+02:00 2020
To: Hal Murray
Subject: Re: Timing via serial port
On 30 Sep 2020, at 18:28, Hal Murray <email@example.com> wrote:
|[Prev in Thread]||Current Thread||[Next in Thread]|