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[Dotgnu-pnet-commits] CVS: pnet/engine md_arm.h, 1.7, 1.8 md_x86.h, 1.5,
|
From: |
Rhys Weatherley <address@hidden> |
|
Subject: |
[Dotgnu-pnet-commits] CVS: pnet/engine md_arm.h, 1.7, 1.8 md_x86.h, 1.5, 1.6 unroll.c, 1.7, 1.8 unroll_arith.c, 1.2, 1.3 |
|
Date: |
Sat, 12 Jul 2003 02:01:19 -0400 |
Update of /cvsroot/dotgnu-pnet/pnet/engine
In directory subversions:/tmp/cvs-serv21431/engine
Modified Files:
md_arm.h md_x86.h unroll.c unroll_arith.c
Log Message:
Unroll some 64-bit integer operations.
Index: md_arm.h
===================================================================
RCS file: /cvsroot/dotgnu-pnet/pnet/engine/md_arm.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -r1.7 -r1.8
*** md_arm.h 12 Jul 2003 03:58:50 -0000 1.7
--- md_arm.h 12 Jul 2003 06:01:17 -0000 1.8
***************
*** 131,134 ****
--- 131,139 ----
/*
+ * Set to 1 if 64-bit register pairs are stored in little-endian order.
+ */
+ #define MD_LITTLE_ENDIAN_LONGS 1
+
+ /*
* Type of the instruction pointer for outputting code.
*/
***************
*** 204,207 ****
--- 209,222 ----
/*
+ * Load a 64-bit word value from an offset from a pointer register
+ * as a pair of 32-bit registers. Only used on 32-bit platforms.
+ */
+ #define md_load_membase_word_64(inst,lreg,hreg,basereg,offset) \
+ do { \
+ arm_load_membase((inst), (lreg), (basereg),
(offset)); \
+ arm_load_membase((inst), (hreg), (basereg),
(offset) + 4); \
+ } while (0)
+
+ /*
* Load a byte value from an offset from a pointer register.
*/
***************
*** 253,256 ****
--- 268,281 ----
/*
+ * Store a pair of 32-bit word registers to an offset from a pointer
+ * register as a 64-bit value. Only used on 32-bit platforms.
+ */
+ #define md_store_membase_word_64(inst,lreg,hreg,basereg,offset) \
+ do { \
+ arm_store_membase((inst), (lreg), (basereg),
(offset)); \
+ arm_store_membase((inst), (hreg), (basereg),
(offset) + 4); \
+ } while (0)
+
+ /*
* Store a byte value to an offset from a pointer register.
*/
***************
*** 334,337 ****
--- 359,385 ----
#define md_ushr_reg_reg_word_32(inst,reg1,reg2) \
arm_shift_reg_reg((inst), ARM_SHR, (reg1), (reg1),
(reg2))
+
+ /*
+ * Perform arithmetic on 64-bit values represented as 32-bit word pairs.
+ */
+ #define md_add_reg_reg_word_64(inst,lreg1,hreg1,lreg2,hreg2) \
+ do { \
+ arm_alu_cc_reg_reg((inst), ARM_ADD, \
+ (lreg1),
(lreg1), (lreg2)); \
+ arm_alu_reg_reg((inst), ARM_ADC, (hreg1),
(hreg1), (hreg2)); \
+ } while (0)
+ #define md_sub_reg_reg_word_64(inst,lreg1,hreg1,lreg2,hreg2) \
+ do { \
+ arm_alu_cc_reg_reg((inst), ARM_SUB, \
+ (lreg1),
(lreg1), (lreg2)); \
+ arm_alu_reg_reg((inst), ARM_SBC, (hreg1),
(hreg1), (hreg2)); \
+ } while (0)
+ #define md_neg_reg_word_64(inst,lreg,hreg) \
+ do { \
+ arm_alu_reg((inst), ARM_MVN, (lreg), (lreg)); \
+ arm_alu_reg((inst), ARM_MVN, (hreg), (hreg)); \
+ arm_alu_cc_reg_imm8((inst), ARM_ADD, (lreg),
(lreg), 1); \
+ arm_alu_reg_imm8((inst), ARM_ADC, (hreg),
(hreg), 0); \
+ } while (0)
/*
Index: md_x86.h
===================================================================
RCS file: /cvsroot/dotgnu-pnet/pnet/engine/md_x86.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -r1.5 -r1.6
*** md_x86.h 12 Jul 2003 04:47:50 -0000 1.5
--- md_x86.h 12 Jul 2003 06:01:17 -0000 1.6
***************
*** 135,138 ****
--- 135,143 ----
/*
+ * Set to 1 if 64-bit register pairs are stored in little-endian order.
+ */
+ #define MD_LITTLE_ENDIAN_LONGS 1
+
+ /*
* Type of the instruction pointer for outputting code.
*/
***************
*** 210,213 ****
--- 215,230 ----
/*
+ * Load a 64-bit word register from an offset from a pointer register
+ * into a pair of 32-bit registers. Only used on 32-bit systems.
+ */
+ #define md_load_membase_word_64(inst,lreg,hreg,basereg,offset) \
+ do { \
+ x86_mov_reg_membase \
+ ((inst), (lreg), (basereg), (offset),
4); \
+ x86_mov_reg_membase \
+ ((inst), (hreg), (basereg), (offset) +
4, 4); \
+ } while (0)
+
+ /*
* Load a byte value from an offset from a pointer register.
*/
***************
*** 259,262 ****
--- 276,291 ----
/*
+ * Store a pair of 32-bit word registers to an offset from a pointer
+ * register as a 64-bit value. Only used on 32-bit systems.
+ */
+ #define md_store_membase_word_64(inst,lreg,hreg,basereg,offset) \
+ do { \
+ x86_mov_membase_reg \
+ ((inst), (basereg), (offset), (lreg),
4); \
+ x86_mov_membase_reg \
+ ((inst), (basereg), (offset) + 4,
(hreg), 4); \
+ } while (0)
+
+ /*
* Store a byte value to an offset from a pointer register.
*/
***************
*** 353,356 ****
--- 382,406 ----
do { (inst) = _md_x86_shift \
((inst), X86_SHR, (reg1), (reg2)); }
while (0)
+
+ /*
+ * Perform arithmetic on 64-bit values represented as 32-bit word pairs.
+ */
+ #define md_add_reg_reg_word_64(inst,lreg1,hreg1,lreg2,hreg2) \
+ do { \
+ x86_alu_reg_reg((inst), X86_ADD, (lreg1),
(lreg2)); \
+ x86_alu_reg_reg((inst), X86_ADC, (hreg1),
(hreg2)); \
+ } while (0)
+ #define md_sub_reg_reg_word_64(inst,lreg1,hreg1,lreg2,hreg2) \
+ do { \
+ x86_alu_reg_reg((inst), X86_SUB, (lreg1),
(lreg2)); \
+ x86_alu_reg_reg((inst), X86_SBB, (hreg1),
(hreg2)); \
+ } while (0)
+ #define md_neg_reg_word_64(inst,lreg,hreg) \
+ do { \
+ x86_not_reg((inst), (lreg)); \
+ x86_not_reg((inst), (hreg)); \
+ x86_alu_reg_imm((inst), X86_ADD, (lreg), 1); \
+ x86_alu_reg_imm((inst), X86_ADC, (hreg), 0); \
+ } while (0)
/*
Index: unroll.c
===================================================================
RCS file: /cvsroot/dotgnu-pnet/pnet/engine/unroll.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -r1.7 -r1.8
*** unroll.c 12 Jul 2003 04:47:50 -0000 1.7
--- unroll.c 12 Jul 2003 06:01:17 -0000 1.8
***************
*** 344,348 ****
#define MD_REG3_32BIT 0x0000
#define MD_REG3_NATIVE 0x0004
! #define MD_REGN_NATIVE 0x0007
/*
--- 344,350 ----
#define MD_REG3_32BIT 0x0000
#define MD_REG3_NATIVE 0x0004
! #define MD_REG4_32BIT 0x0000
! #define MD_REG4_NATIVE 0x0008
! #define MD_REGN_NATIVE 0x000F
/*
***************
*** 818,821 ****
--- 820,925 ----
}
+ #ifdef IL_NATIVE_INT32
+
+ /*
+ * Get the four top-most word values on the stack into registers.
+ * "reg1" will be the lowest of the four.
+ */
+ static void GetTopFourWordRegisters(MDUnroll *unroll,
+ int
*reg1, int *reg2,
+ int
*reg3, int *reg4,
+ int
flags)
+ {
+ /* Clear the cached local information */
+ unroll->cachedLocal = -1;
+ unroll->cachedReg = -1;
+
+ /* See if we already have four word registers in play */
+ if(unroll->pseudoStackSize > 3)
+ {
+ *reg1 = unroll->pseudoStack[unroll->pseudoStackSize - 4];
+ if(!MD_IS_FREG(*reg1))
+ {
+ *reg2 = unroll->pseudoStack[unroll->pseudoStackSize -
3];
+ if(!MD_IS_FREG(*reg2))
+ {
+ *reg3 =
unroll->pseudoStack[unroll->pseudoStackSize - 2];
+ if(!MD_IS_FREG(*reg3))
+ {
+ *reg4 =
unroll->pseudoStack[unroll->pseudoStackSize - 1];
+ if(!MD_IS_FREG(*reg4))
+ {
+ *reg1 &= ~MD_NATIVE_REG_MASK;
+ *reg2 &= ~MD_NATIVE_REG_MASK;
+ *reg3 &= ~MD_NATIVE_REG_MASK;
+ *reg4 &= ~MD_NATIVE_REG_MASK;
+ return;
+ }
+ }
+ }
+ }
+ }
+
+ /* See if we have three word registers in play */
+ if(unroll->pseudoStackSize == 3)
+ {
+ *reg2 = unroll->pseudoStack[0];
+ *reg3 = unroll->pseudoStack[1];
+ *reg4 = unroll->pseudoStack[2];
+ if(!MD_IS_FREG(*reg2) && !MD_IS_FREG(*reg3) &&
!MD_IS_FREG(*reg4))
+ {
+ *reg1 = RollRegisterStack(unroll, flags &
MD_REG1_NATIVE, -1);
+ *reg2 &= ~MD_NATIVE_REG_MASK;
+ *reg3 &= ~MD_NATIVE_REG_MASK;
+ *reg4 &= ~MD_NATIVE_REG_MASK;
+ return;
+ }
+ }
+
+ /* See if we have two word registers in play */
+ if(unroll->pseudoStackSize == 2)
+ {
+ *reg3 = unroll->pseudoStack[0];
+ *reg4 = unroll->pseudoStack[1];
+ if(!MD_IS_FREG(*reg3) && !MD_IS_FREG(*reg4))
+ {
+ *reg4 &= ~MD_NATIVE_REG_MASK;
+ *reg3 &= ~MD_NATIVE_REG_MASK;
+ *reg2 = RollRegisterStack(unroll, flags &
MD_REG2_NATIVE, -1);
+ *reg1 = RollRegisterStack(unroll, flags &
MD_REG1_NATIVE, -1);
+ return;
+ }
+ }
+
+ /* See if we have one word register in play */
+ if(unroll->pseudoStackSize == 1)
+ {
+ *reg4 = unroll->pseudoStack[0];
+ if(!MD_IS_FREG(*reg4))
+ {
+ *reg4 &= ~MD_NATIVE_REG_MASK;
+ *reg3 = RollRegisterStack(unroll, flags &
MD_REG3_NATIVE, -1);
+ *reg2 = RollRegisterStack(unroll, flags &
MD_REG2_NATIVE, -1);
+ *reg1 = RollRegisterStack(unroll, flags &
MD_REG1_NATIVE, -1);
+ return;
+ }
+ }
+
+ /* We may have an FP register in play, so flush it */
+ FlushRegisterStack(unroll);
+
+ /* Load the top of the CVM stack into the first four registers */
+ RollRegisterStack(unroll, flags & MD_REG4_NATIVE, regAllocOrder[3]);
+ RollRegisterStack(unroll, flags & MD_REG3_NATIVE, regAllocOrder[2]);
+ RollRegisterStack(unroll, flags & MD_REG2_NATIVE, regAllocOrder[1]);
+ RollRegisterStack(unroll, flags & MD_REG1_NATIVE, regAllocOrder[0]);
+ *reg1 = (unroll->pseudoStack[0] & ~MD_NATIVE_REG_MASK);
+ *reg2 = (unroll->pseudoStack[1] & ~MD_NATIVE_REG_MASK);
+ *reg3 = (unroll->pseudoStack[2] & ~MD_NATIVE_REG_MASK);
+ *reg4 = (unroll->pseudoStack[3] & ~MD_NATIVE_REG_MASK);
+ }
+
+ #endif /* IL_NATIVE_INT32 */
+
#ifdef MD_HAS_FP
***************
*** 1407,1410 ****
--- 1511,1517 ----
md_inst_ptr unrollStart;
int reg, reg2, reg3;
+ #ifdef IL_NATIVE_INT32
+ int reg4;
+ #endif
ILCachePosn posn;
Index: unroll_arith.c
===================================================================
RCS file: /cvsroot/dotgnu-pnet/pnet/engine/unroll_arith.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -r1.2 -r1.3
*** unroll_arith.c 12 Jul 2003 04:47:50 -0000 1.2
--- unroll_arith.c 12 Jul 2003 06:01:17 -0000 1.3
***************
*** 174,177 ****
--- 174,330 ----
break;
+ case COP_LADD:
+ {
+ /* Add 64-bit integers */
+ UNROLL_START();
+ #ifdef IL_NATIVE_INT32
+ GetTopFourWordRegisters(&unroll, ®, ®2, ®3, ®4,
+ MD_REG1_32BIT |
MD_REG2_32BIT |
+ MD_REG3_32BIT |
MD_REG4_32BIT);
+ #if MD_LITTLE_ENDIAN_LONGS
+ md_add_reg_reg_word_64(unroll.out, reg, reg2, reg3, reg4);
+ #else
+ md_add_reg_reg_word_64(unroll.out, reg2, reg, reg4, reg3);
+ #endif
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ #else
+ GetTopTwoWordRegisters(&unroll, ®, ®2,
+ MD_REG1_NATIVE |
MD_REG2_NATIVE);
+ md_add_reg_reg_word_native(unroll.out, reg, reg2);
+ FreeTopRegister(&unroll, -1);
+ #endif
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+ }
+ break;
+
+ case COP_LSUB:
+ {
+ /* Subtract 64-bit integers */
+ UNROLL_START();
+ #ifdef IL_NATIVE_INT32
+ GetTopFourWordRegisters(&unroll, ®, ®2, ®3, ®4,
+ MD_REG1_32BIT |
MD_REG2_32BIT |
+ MD_REG3_32BIT |
MD_REG4_32BIT);
+ #if MD_LITTLE_ENDIAN_LONGS
+ md_sub_reg_reg_word_64(unroll.out, reg, reg2, reg3, reg4);
+ #else
+ md_sub_reg_reg_word_64(unroll.out, reg2, reg, reg4, reg3);
+ #endif
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ #else
+ GetTopTwoWordRegisters(&unroll, ®, ®2,
+ MD_REG1_NATIVE |
MD_REG2_NATIVE);
+ md_sub_reg_reg_word_native(unroll.out, reg, reg2);
+ FreeTopRegister(&unroll, -1);
+ #endif
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+ }
+ break;
+
+ case COP_LAND:
+ {
+ /* Bitwise AND 64-bit integers */
+ UNROLL_START();
+ #ifdef IL_NATIVE_INT32
+ GetTopFourWordRegisters(&unroll, ®, ®2, ®3, ®4,
+ MD_REG1_32BIT |
MD_REG2_32BIT |
+ MD_REG3_32BIT |
MD_REG4_32BIT);
+ md_and_reg_reg_word_32(unroll.out, reg, reg3);
+ md_and_reg_reg_word_32(unroll.out, reg2, reg4);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ #else
+ GetTopTwoWordRegisters(&unroll, ®, ®2,
+ MD_REG1_NATIVE |
MD_REG2_NATIVE);
+ md_add_reg_reg_word_native(unroll.out, reg, reg2);
+ FreeTopRegister(&unroll, -1);
+ #endif
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+ }
+ break;
+
+ case COP_LOR:
+ {
+ /* Bitwise OR 64-bit integers */
+ UNROLL_START();
+ #ifdef IL_NATIVE_INT32
+ GetTopFourWordRegisters(&unroll, ®, ®2, ®3, ®4,
+ MD_REG1_32BIT |
MD_REG2_32BIT |
+ MD_REG3_32BIT |
MD_REG4_32BIT);
+ md_or_reg_reg_word_32(unroll.out, reg, reg3);
+ md_or_reg_reg_word_32(unroll.out, reg2, reg4);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ #else
+ GetTopTwoWordRegisters(&unroll, ®, ®2,
+ MD_REG1_NATIVE |
MD_REG2_NATIVE);
+ md_or_reg_reg_word_native(unroll.out, reg, reg2);
+ FreeTopRegister(&unroll, -1);
+ #endif
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+ }
+ break;
+
+ case COP_LXOR:
+ {
+ /* Bitwise XOR 64-bit integers */
+ UNROLL_START();
+ #ifdef IL_NATIVE_INT32
+ GetTopFourWordRegisters(&unroll, ®, ®2, ®3, ®4,
+ MD_REG1_32BIT |
MD_REG2_32BIT |
+ MD_REG3_32BIT |
MD_REG4_32BIT);
+ md_xor_reg_reg_word_32(unroll.out, reg, reg3);
+ md_xor_reg_reg_word_32(unroll.out, reg2, reg4);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ #else
+ GetTopTwoWordRegisters(&unroll, ®, ®2,
+ MD_REG1_NATIVE |
MD_REG2_NATIVE);
+ md_xor_reg_reg_word_native(unroll.out, reg, reg2);
+ FreeTopRegister(&unroll, -1);
+ #endif
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+ }
+ break;
+
+ case COP_LNEG:
+ {
+ /* Negate a 64-bit integer */
+ UNROLL_START();
+ #ifdef IL_NATIVE_INT32
+ GetTopTwoWordRegisters(&unroll, ®, ®2,
+ MD_REG1_32BIT |
MD_REG2_32BIT);
+ #if MD_LITTLE_ENDIAN_LONGS
+ md_neg_reg_word_64(unroll.out, reg, reg2);
+ #else
+ md_neg_reg_word_64(unroll.out, reg2, reg);
+ #endif
+ #else
+ reg = GetTopWordRegister(&unroll, MD_REG1_NATIVE);
+ md_neg_reg_word_native(unroll.out, reg);
+ #endif
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+ }
+ break;
+
+ case COP_LNOT:
+ {
+ /* Bitwise NOT a 64-bit integer */
+ UNROLL_START();
+ #ifdef IL_NATIVE_INT32
+ GetTopTwoWordRegisters(&unroll, ®, ®2,
+ MD_REG1_32BIT |
MD_REG2_32BIT);
+ md_not_reg_word_32(unroll.out, reg);
+ md_not_reg_word_32(unroll.out, reg2);
+ #else
+ reg = GetTopWordRegister(&unroll, MD_REG1_NATIVE);
+ md_not_reg_word_native(unroll.out, reg);
+ #endif
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+ }
+ break;
+
#ifdef MD_HAS_FP
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