|
| From: | Rhys Weatherley <address@hidden> |
| Subject: | [Dotgnu-pnet-commits] CVS: pnet/engine arm_codegen.h,1.2,1.3 |
| Date: | Fri, 11 Jul 2003 07:18:14 -0400 |
Update of /cvsroot/dotgnu-pnet/pnet/engine
In directory subversions:/tmp/cvs-serv17670/engine
Modified Files:
arm_codegen.h
Log Message:
Macro expansion bugs on ARM.
Index: arm_codegen.h
===================================================================
RCS file: /cvsroot/dotgnu-pnet/pnet/engine/arm_codegen.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -r1.2 -r1.3
*** arm_codegen.h 21 May 2003 07:14:06 -0000 1.2
--- arm_codegen.h 11 Jul 2003 11:18:11 -0000 1.3
***************
*** 182,207 ****
#define arm_alu_reg_imm(inst,opc,dreg,sreg,imm) \
do { \
! int __value = (int)(imm); \
! if(__value >= 0 && __value < 256) \
{ \
! arm_alu_reg_imm8((inst), (opc), (dreg),
(sreg), __value); \
} \
else \
{ \
(inst) = _arm_alu_reg_imm \
! ((inst), (opc), (dreg), (sreg),
__value, 0); \
} \
} while (0)
#define arm_alu_reg_imm_save_work(inst,opc,dreg,sreg,imm) \
do { \
! int __value = (int)(imm); \
! if(__value >= 0 && __value < 256) \
{ \
! arm_alu_reg_imm8((inst), (opc), (dreg),
(sreg), __value); \
} \
else \
{ \
(inst) = _arm_alu_reg_imm \
! ((inst), (opc), (dreg), (sreg),
__value, 1); \
} \
} while (0)
--- 182,209 ----
#define arm_alu_reg_imm(inst,opc,dreg,sreg,imm) \
do { \
! int __alu_imm = (int)(imm); \
! if(__alu_imm >= 0 && __alu_imm < 256) \
{ \
! arm_alu_reg_imm8 \
! ((inst), (opc), (dreg), (sreg),
__alu_imm); \
} \
else \
{ \
(inst) = _arm_alu_reg_imm \
! ((inst), (opc), (dreg), (sreg),
__alu_imm, 0); \
} \
} while (0)
#define arm_alu_reg_imm_save_work(inst,opc,dreg,sreg,imm) \
do { \
! int __alu_imm_save = (int)(imm); \
! if(__alu_imm_save >= 0 && __alu_imm_save < 256)
\
{ \
! arm_alu_reg_imm8 \
! ((inst), (opc), (dreg), (sreg),
__alu_imm_save); \
} \
else \
{ \
(inst) = _arm_alu_reg_imm \
! ((inst), (opc), (dreg), (sreg),
__alu_imm_save, 1); \
} \
} while (0)
***************
*** 261,272 ****
#define arm_test_reg_imm(inst,opc,sreg,imm) \
do { \
! int __value = (int)(imm); \
! if(__value >= 0 && __value < 256) \
{ \
! arm_alu_cc_reg_imm8((inst), (opc), 0,
(sreg), __value); \
} \
else \
{ \
! arm_mov_reg_imm((inst), ARM_WORK,
__value); \
arm_test_reg_reg((inst), (opc), (sreg),
ARM_WORK); \
} \
--- 263,274 ----
#define arm_test_reg_imm(inst,opc,sreg,imm) \
do { \
! int __test_imm = (int)(imm); \
! if(__test_imm >= 0 && __test_imm < 256) \
{ \
! arm_alu_cc_reg_imm8((inst), (opc), 0,
(sreg), __test_imm); \
} \
else \
{ \
! arm_mov_reg_imm((inst), ARM_WORK,
__test_imm); \
arm_test_reg_reg((inst), (opc), (sreg),
ARM_WORK); \
} \
***************
*** 298,319 ****
#define arm_mov_reg_imm(inst,reg,imm) \
do { \
! int __value = (int)(imm); \
! if(__value >= 0 && __value < 256) \
{ \
! arm_mov_reg_imm8((inst), (reg),
__value); \
} \
else if((reg) == ARM_PC) \
{ \
! (inst) = _arm_mov_reg_imm((inst),
ARM_WORK, __value); \
arm_mov_reg_reg((inst), ARM_PC,
ARM_WORK); \
} \
! else if(__value > -256 && __value < 0) \
{ \
! arm_mov_reg_imm8((inst), (reg),
~(__value)); \
arm_alu_reg((inst), ARM_MVN, (reg),
(reg)); \
} \
else \
{ \
! (inst) = _arm_mov_reg_imm((inst),
(reg), __value); \
} \
} while (0)
--- 300,321 ----
#define arm_mov_reg_imm(inst,reg,imm) \
do { \
! int __imm = (int)(imm); \
! if(__imm >= 0 && __imm < 256) \
{ \
! arm_mov_reg_imm8((inst), (reg), __imm);
\
} \
else if((reg) == ARM_PC) \
{ \
! (inst) = _arm_mov_reg_imm((inst),
ARM_WORK, __imm); \
arm_mov_reg_reg((inst), ARM_PC,
ARM_WORK); \
} \
! else if(__imm > -256 && __imm < 0) \
{ \
! arm_mov_reg_imm8((inst), (reg),
~(__imm)); \
arm_alu_reg((inst), ARM_MVN, (reg),
(reg)); \
} \
else \
{ \
! (inst) = _arm_mov_reg_imm((inst),
(reg), __imm); \
} \
} while (0)
***************
*** 397,403 ****
#define arm_branch(inst,cond,target) \
do { \
! int __offset = (int)(((unsigned char
*)(target)) - \
! (((unsigned
char *)(inst)) + 8)); \
! arm_branch_imm((inst), (cond), __offset); \
} while (0)
#define arm_jump(inst,target) arm_branch((inst), ARM_CC_AL, (target))
--- 399,405 ----
#define arm_branch(inst,cond,target) \
do { \
! int __br_offset = (int)(((unsigned char
*)(target)) - \
! (((unsigned
char *)(inst)) + 8)); \
! arm_branch_imm((inst), (cond), __br_offset); \
} while (0)
#define arm_jump(inst,target) arm_branch((inst), ARM_CC_AL, (target))
***************
*** 409,417 ****
#define arm_jump_long(inst,target) \
do { \
! int __offset = (int)(((unsigned char
*)(target)) - \
! (((unsigned
char *)(inst)) + 8)); \
! if(__offset >= -0x04000000 && __offset <
0x04000000) \
{ \
! arm_jump_imm((inst), __offset); \
} \
else \
--- 411,419 ----
#define arm_jump_long(inst,target) \
do { \
! int __jmp_offset = (int)(((unsigned char
*)(target)) - \
! (((unsigned
char *)(inst)) + 8)); \
! if(__jmp_offset >= -0x04000000 && __jmp_offset
< 0x04000000) \
{ \
! arm_jump_imm((inst), __jmp_offset); \
} \
else \
***************
*** 426,433 ****
#define arm_patch(inst,target) \
do { \
! int __offset = (int)(((unsigned char
*)(target)) - \
! (((unsigned
char *)(inst)) + 8)); \
! __offset = (__offset >> 2) & 0x00FFFFFF; \
! *((int *)(inst)) = (*((int *)(inst)) &
0xFF000000) | __offset; \
} while (0)
--- 428,436 ----
#define arm_patch(inst,target) \
do { \
! int __p_offset = (int)(((unsigned char
*)(target)) - \
! (((unsigned
char *)(inst)) + 8)); \
! __p_offset = (__p_offset >> 2) & 0x00FFFFFF; \
! *((int *)(inst)) = (*((int *)(inst)) &
0xFF000000) | \
! __p_offset; \
} while (0)
***************
*** 447,455 ****
#define arm_call(inst,target) \
do { \
! int __offset = (int)(((unsigned char
*)(target)) - \
! (((unsigned
char *)(inst)) + 8)); \
! if(__offset >= -0x04000000 && __offset <
0x04000000) \
{ \
! arm_call_imm((inst), __offset); \
} \
else \
--- 450,458 ----
#define arm_call(inst,target) \
do { \
! int __call_offset = (int)(((unsigned char
*)(target)) - \
!
(((unsigned char *)(inst)) + 8)); \
! if(__call_offset >= -0x04000000 &&
__call_offset < 0x04000000) \
{ \
! arm_call_imm((inst), __call_offset); \
} \
else \
***************
*** 504,525 ****
#define arm_load_membase_either(inst,reg,basereg,imm,mask) \
do { \
! int __offset = (int)(imm); \
! if(__offset >= 0 && __offset < (1 << 12)) \
{ \
*(inst)++ = arm_prefix(0x05900000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
(((unsigned
int)(reg)) << 12) | \
! ((unsigned
int)__offset); \
} \
! else if(__offset > -(1 << 12) && __offset < 0) \
{ \
*(inst)++ = arm_prefix(0x05100000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
(((unsigned
int)(reg)) << 12) | \
! ((unsigned
int)(-__offset)); \
} \
else \
{ \
! arm_mov_reg_imm((inst), ARM_WORK,
__offset); \
*(inst)++ = arm_prefix(0x07900000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
--- 507,528 ----
#define arm_load_membase_either(inst,reg,basereg,imm,mask) \
do { \
! int __mb_offset = (int)(imm); \
! if(__mb_offset >= 0 && __mb_offset < (1 << 12))
\
{ \
*(inst)++ = arm_prefix(0x05900000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
(((unsigned
int)(reg)) << 12) | \
! ((unsigned
int)__mb_offset); \
} \
! else if(__mb_offset > -(1 << 12) && __mb_offset
< 0) \
{ \
*(inst)++ = arm_prefix(0x05100000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
(((unsigned
int)(reg)) << 12) | \
! ((unsigned
int)(-__mb_offset)); \
} \
else \
{ \
! arm_mov_reg_imm((inst), ARM_WORK,
__mb_offset); \
*(inst)++ = arm_prefix(0x07900000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
***************
*** 567,588 ****
#define arm_store_membase_either(inst,reg,basereg,imm,mask) \
do { \
! int __offset = (int)(imm); \
! if(__offset >= 0 && __offset < (1 << 12)) \
{ \
*(inst)++ = arm_prefix(0x05800000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
(((unsigned
int)(reg)) << 12) | \
! ((unsigned
int)__offset); \
} \
! else if(__offset > -(1 << 12) && __offset < 0) \
{ \
*(inst)++ = arm_prefix(0x05000000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
(((unsigned
int)(reg)) << 12) | \
! ((unsigned
int)(-__offset)); \
} \
else \
{ \
! arm_mov_reg_imm((inst), ARM_WORK,
__offset); \
*(inst)++ = arm_prefix(0x07800000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
--- 570,591 ----
#define arm_store_membase_either(inst,reg,basereg,imm,mask) \
do { \
! int __sm_offset = (int)(imm); \
! if(__sm_offset >= 0 && __sm_offset < (1 << 12))
\
{ \
*(inst)++ = arm_prefix(0x05800000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
(((unsigned
int)(reg)) << 12) | \
! ((unsigned
int)__sm_offset); \
} \
! else if(__sm_offset > -(1 << 12) && __sm_offset
< 0) \
{ \
*(inst)++ = arm_prefix(0x05000000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
(((unsigned
int)(reg)) << 12) | \
! ((unsigned
int)(-__sm_offset)); \
} \
else \
{ \
! arm_mov_reg_imm((inst), ARM_WORK,
__sm_offset); \
*(inst)++ = arm_prefix(0x07800000 |
(mask)) | \
(((unsigned
int)(basereg)) << 16) | \
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