[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[dmidecode] [PATCH] dmidecode: Support new format of Processor ID from S
From: |
Nhi Pham |
Subject: |
[dmidecode] [PATCH] dmidecode: Support new format of Processor ID from SMBIOS 3.4.0 |
Date: |
Tue, 17 Aug 2021 20:04:40 +0700 |
For ARM64-class CPUs, the format of the Processor ID field depends on
the processor's support of the SMCCC_ARCH_SOC_ID architectural call.
This supports decoding the Processor ID correctly in case the SoC ID is
supported. This patch should work for ARM32-class CPUs also.
Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
---
dmidecode.c | 39 ++++++++++++++++++++++++++++-----------
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/dmidecode.c b/dmidecode.c
index 69ea0e8..a44f969 100644
--- a/dmidecode.c
+++ b/dmidecode.c
@@ -1126,18 +1126,35 @@ static void dmi_processor_id(const struct dmi_header *h)
else if ((type >= 0x100 && type <= 0x101) /* ARM */
|| (type >= 0x118 && type <= 0x119)) /* ARM */
{
- u32 midr = DWORD(p);
+ u64 id = QWORD(p);
/*
- * The format of this field was not defined for ARM processors
- * before version 3.1.0 of the SMBIOS specification, so we
- * silently skip it if it reads all zeroes.
- */
- if (midr == 0)
- return;
- pr_attr("Signature",
- "Implementor 0x%02x, Variant 0x%x, Architecture %u,
Part 0x%03x, Revision %u",
- midr >> 24, (midr >> 20) & 0xF,
- (midr >> 16) & 0xF, (midr >> 4) & 0xFFF, midr & 0xF);
+ * The field's format depends on the processor's support of
+ * the SMCCC_ARCH_SOC_ID architectural call. Software can
determine
+ * the support for SoC ID by examining the Processor
Characteristicsfield
+ * for "Arm64 SoC ID" bit.
+ */
+ if (((WORD(data + 0x26) & 0x200) >> 9) != 0)
+ {
+ /*
+ * If Soc ID is supported, the first DWORD is the
JEP-106 code;
+ * the second DWORD is the SoC revision value.
+ */
+ pr_attr("Signature",
+ "JEP-106 Code 0x%02X%02X, SoC ID 0x%02X, SoC
Revision 0x%X",
+ (id.h >> 24) & 0x7F, (id.h >> 16) & 0xFF, id.h
& 0xF, id.l);
+ } else {
+ /*
+ * The format of this field was not defined for ARM
processors
+ * before version 3.1.0 of the SMBIOS specification, so
we
+ * silently skip it if it reads all zeroes.
+ */
+ if (id.l == 0)
+ return;
+ pr_attr("Signature",
+ "Implementor 0x%02x, Variant 0x%x, Architecture
%u, Part 0x%03x, Revision %u",
+ id.l >> 24, (id.l >> 20) & 0xF,
+ (id.l >> 16) & 0xF, (id.l >> 4) & 0xFFF, id.l &
0xF);
+ }
return;
}
else if ((type >= 0x0B && type <= 0x15) /* Intel, Cyrix */
--
2.17.1
- [dmidecode] [PATCH] dmidecode: Support new format of Processor ID from SMBIOS 3.4.0,
Nhi Pham <=