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[Discuss-gnuradio] [GSoC19]: Weekly report of cycle-accurate Verilog sim

From: Bowen Hu
Subject: [Discuss-gnuradio] [GSoC19]: Weekly report of cycle-accurate Verilog simulation
Date: Sun, 19 May 2019 16:09:15 +0000

Hi all,

Here(https://b0wen-hu.github.io/2019/05/19/GSoC-weekly-report-2/) is my report this week.

## Progress this week
I have finished the tutorials from chapter 2 to chapter 6 this week.

I changed the module name gr-howto to gr-mytutorial.

## Plan next week
Finish the tutorials chapter 7 left in the next week.

Try to make the Verilator related header file available in GNU Radio blocks.

## Issue(s)
Verilator will compile Verilog file into C++, we could run simulation with the class it offers. But we do not know the member names(ports of Verilog module) in that class unless we have some way to parse either Verilator-generated C++ file or Verilog source file (Verilator do offer a XML file output which contains the class name, but this file changes with version of Verilator according to the author.). Due to the lack of reflection mechanism in C++, I may have to write the class names right in to code of simulation.

I need to extract the ports name which is clk rst_n dout in flicker.v. I am not sure, would it be appropriate if I just use regular _expression_ to read the C++ header file.

Best regards,

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