Re: [Discuss-gnuradio] Using PPS as a sampling trigger

[Josh Blum]

> The problem I am having right now is that the timing information is not
> matching up to the signal I am inputting to the PPS port.  I started off
> with inputting a signal that has an IPP of 1ms, but each PPS Trigger output
> incremented in values of 5ms.  I made additional changes to the input signal
> by making the IPP 5ms, then the increment of the printed PPS trigger was 10
> ms.  Inside each IPP there are also some trigger variations, but these were
> never detected.  Is there something I am not doing correctly in my code in
> order to detect each PPS trigger? It seems like once a PPS is detected, the
> program assumes each subsequent PPS will occur in equal time increments.
> Please let me know what you think. 
> 

This method of polling get_time_last_pps() is only going to work if you
are pulsing the input "slowly" enough. You can measure the duration of a
read by calling get_time_now() twice and calculating the difference in
time. If you cant satisfy this condition, then I can suggest a few other
mods that should work for you.

1) Pass the trigger input along with the sample stream as the lowest
bit. This would be an FPGA mod replacing the DDC's input.

Basically, you monitor the sample for when this bit goes high/low to
know which samples where triggered on.

1.1) A slight variation on this would be to use the second RX DSP chain
to sample the trigger. Replace the ADC input to the DDC with the trigger.

http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/top/N2x0/u2plus_core.v#L612

2) Use jcorgan's gpio branch. This mod produces an async packet with
timestamp when the state of the GPIOs changes. For this you might use
one of the daughterboard GPIOs rather than PPS input for the trigger
(unless you mod it).

http://gnuradio.org/cgit/jcorgan-uhd.git/log/?h=gpio

For this option, you read the async message queue for events to
determine which times refer to triggered sample events.

3) And other FPGA mod option: Use the trigger to "&&" with this
run-signal assignment:
http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/top/N2x0/u2plus_core.v#L584

For this mod to work, you will need to issue "finite" stream commands
such that the number of samples requested is less than the duration of
your trigger activation duration. You will only see packets that start
exactly on the trigger event.

-Josh