Re: [Discuss-gnuradio] sign_extend.v !!!!

[bobb]

>-----Original Message-----
>From: Josh Blum [mailto:address@hidden
>Sent: Sunday, March 13, 2011 10:52 PM
>To: address@hidden
>Subject: Re: [Discuss-gnuradio] sign_extend.v !!!!
>
>http://en.wikipedia.org/wiki/Sign_extension

 <website that explains what it means to sign extend - this is what this module 
does - more detailed explanation as to how it does it appears below>

>On 03/13/2011 07:47 PM, Alaa Salaheldin wrote:
>> Can anyone please help me to understand what's going on in sign_extend.v ,
>> this macro is initiated in the cic_decim.v
>> 
>> sign_extend #(bw,bw+maxbitgain)
>>       ext_input (.in(signal_in),.out(signal_in_ext));
>> 

instantiates the sign_extend module. Positional parameter settings "#(bw, bw + 
maxbitgain)" will be assigned to bits_in and bits_out, respectively.

>> 
>> when i opened the macro i couldn't understand it's function
>> 
>> // Sign extension "macro"
>> // bits_out should be greater than bits_in
>> 
>> module sign_extend (in,out);

module with 2 ports: in & out

>> parameter bits_in=0;  // FIXME Quartus insists on a default
>> parameter bits_out=0;
>>  input [bits_in-1:0] in;

size of input port "in" is determined by "bits_in"

>> output [bits_out-1:0] out;

size of output port "out" is determined by "bits_out"

>>  assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};

this expression assigns a value to out using both concatenation & replication

  {(bits_out-bits_in){in[bits_in-1]}} replicates in's MSB (bits_out - bits_in) 
times. This value is then prepended (via concatenation) to in.

  Voila! Sign extension implemented in verilog and explained in the webpage 
Josh pointed to above.

>> endmodule
>> 
>> Thanks in advance.

  Hope this helps,

  --Bob