[Discuss-gnuradio] Is it possible to change the sampling rate of D/A converter

[Yan Nie]

Dear all,

Is it possible to change the sampling rate of D/A converter to 64MHz? I saw the sampling rate of D/A converter is defined in usrp_basic.cc, which is fpga_master_clock_freq() * 2. Is it possible to make the master clock frequency not multiply by 2? Can it be changed in python when the flow gragh for the whole system is built.

Thank you so much in advance.

Regards,
Yan

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