Re: [Discuss-gnuradio] USRP1 Testbench Question

[Catalin Patulea]

On Mon, May 17, 2010 at 12:00 PM,  <address@hidden> wrote:
> Date: Sun, 16 May 2010 10:20:51 -0700 (PDT)
> From: D V <address@hidden>
> Subject: [Discuss-gnuradio] USRP1 Testbench Question
> To: address@hidden
> Message-ID: <address@hidden>
> Content-Type: text/plain; charset=us-ascii
>
> [...]
> I made a (hilariously naive) attempt at writing my own testbench using 
> Xilinx's ISim, associated with usrp_std, linking 64 Mhz and 48 Mhz clocks to 
> master_clk and usbclk, respectively, inputting a square wave on the rx_a_a 
> bus, and holding usbctl lines OE and RD high. When I do all this, the usbdata 
> bus goes from 16'Z to 16'0, when RD and OE are
> enabled, but that's about it. I would imagine that there are all sorts of 
> other registers that I would need to send commands to, maybe over the SDI/SDO 
> or io_rx lines, to get a response from the FPGA firmware, but after looking 
> at the FAQs I'm not quite sure where to start. I've included this testbench 
> code below, if anybody would care to comment on what else is needed to 
> initialize USRP1; or if someone could tell me where I could find a detailed 
> discussion on writing a testbench for usrp_std that's already online, I would 
> be very grateful.

Hi Bardus,

I think I can offer some insights into this porting process as ThinkRF
has done this for a Spartan 3E. Know however that I have not done any
work on the testbenches. The ported design does work though :)

First off, it's good to keep in mind that there are two clock domains
in this design. The digital downconverter (DDC) runs in the ADC clock
domain, SPI runs in the USB domain.

Some clock configurations on the 1600E lead to some sort of
interference which basically butchers your clocks. If in doubt about
your clocks, feed them to a single toggle flip-flop and check with a
scope that your output is nice and clean. (Feeding the clock directly
to an I/O leads to the usage of regular lines instead of the
"low-skew" dedicated clock lines. I've only observed strange behaviour
on these dedicated clock lines.)

Next up: SPI. Most likely the reason you weren't seeing anything on
usbdata is the DDC was unconfigured. This is indeed done through SPI
(usbdata is used only for data, no control). Check that your SPI is
working by reading register 4, which should be hardcoded to a constant
in your top module. You will become intimately familiar with
usrp_prims during this part of the process. At a higher level, actual
DDC configuration is done by
usrp/host/lib/{usrp_basic,usrp_standard}.cc.

Moving data from the FPGA's FIFO to the Cypress FX2's FIFO is done by
an FX2 peripheral called the GPIF (General-Purpose InterFace). It's
basically a glorified programmable state machine which handles flow
control on the FX2<->FPGA bus. It's badly documented and the tool
Cypress provides for configuring it sucks, but hopefully it "just
works" for you with what's already in the repo.

Other than that, expect little hiccups along the way.. I found it not
too hard to understand at a high level but once you drill down there
are lots of things that can go wrong. A few LEDs and a header where
you can route FPGA internal signals are indispensable.

Good luck!

Catalin