Well, it seems the aeMB guys are working on a new version of the the
core. Maybe the new core will perform better.
Em 14 de maio de 2010 18:17, Brian Padalino <address@hidden
<mailto:address@hidden>> escreveu:
2010/5/14 Tiago Rogério Mück <address@hidden
<mailto:address@hidden>>:
> Hello,
>
> It seems that everyone is having troubles with ISE 11.x, but has
anyone
> tried the new ISE 12 ?
>
> We have successfully synthesized the USRP2 fpga code with ISE
12.1, but we
> got a timing error and the bitstream didn't seem to work:
find_usrps didn't
> find anything and the leds didn't flash.
>
> We are using the latest code from the repositories for both fpga and
> firmware.
>
> Is there anyone who has tried ISE 12 and want to share the
experience ?
I am not building the USRP2 FPGA, or have experience with ISE 12, but
the errors you have are all related to BRAM feeding the aeMB CPU -
more specifically RAM output -> Mux -> Adder -> FF, mostly with 7 to
10 layers of logic inbetween.
Good luck debugging that portion of the CPU. Hopefully you can
achieve timing closure.
Brian
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