[Commit-gnuradio] r10103 - in gnuradio/trunk/usrp2: firmware/lib fpga/timing

[matt]

Author: matt
Date: 2008-12-04 17:36:22 -0700 (Thu, 04 Dec 2008)
New Revision: 10103

Modified:
   gnuradio/trunk/usrp2/firmware/lib/memory_map.h
   gnuradio/trunk/usrp2/fpga/timing/time_sync.v
Log:
implemented "reset master clock on next PPS" so we can easily sync multiple 
units without MIMO connections


Modified: gnuradio/trunk/usrp2/firmware/lib/memory_map.h
===================================================================
--- gnuradio/trunk/usrp2/firmware/lib/memory_map.h      2008-12-05 00:03:29 UTC 
(rev 10102)
+++ gnuradio/trunk/usrp2/firmware/lib/memory_map.h      2008-12-05 00:36:22 UTC 
(rev 10103)
@@ -622,6 +622,7 @@
   volatile uint32_t tick_control;
   volatile uint32_t tick_interval;
   volatile uint32_t delta_time;
+  volatile uint32_t sync_on_next_pps;
 } timesync_regs_t;
 
 #define timesync_regs ((timesync_regs_t *) TIMESYNC_BASE)

Modified: gnuradio/trunk/usrp2/fpga/timing/time_sync.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/timing/time_sync.v        2008-12-05 00:03:29 UTC 
(rev 10102)
+++ gnuradio/trunk/usrp2/fpga/timing/time_sync.v        2008-12-05 00:36:22 UTC 
(rev 10103)
@@ -18,6 +18,7 @@
    wire        tick_free_run;
    reg                tick_int_enable, tick_source, external_sync;
    reg [31:0]  tick_interval;
+   reg                sync_on_next_pps;
    
    // Generate master time
    always @(posedge sys_clk_i)
@@ -25,6 +26,8 @@
        master_time <= 0;
      else if(external_sync & sync_rcvd)
        master_time <= master_time_rcvd + delta_time;
+     else if(pps_ext & sync_on_next_pps)
+       master_time <= 0;
      else
        master_time <= master_time + 1;
    assign      master_time_o = master_time;
@@ -42,7 +45,10 @@
       .exp_pps_in(exp_pps_in) );
 
    assign     ack_o = stb_i;
-
+   wire       wb_write = cyc_i & stb_i & we_i;
+   wire       wb_read = cyc_i & stb_i & ~we_i;
+   wire       wb_acc = cyc_i & stb_i;
+   
    always @(posedge wb_clk_i)
      if(rst_i)
        begin
@@ -52,17 +58,30 @@
          tick_interval <= 100000-1;  // default to 1K times per second
          delta_time <= 0;
        end
-     else if(stb_i & we_i)
-       if(adr_i[2:0] == 2)
-        delta_time <= dat_i;
-       else if(adr_i[2:0] == 1)
-        tick_interval <= dat_i;
-       else
-        begin
-           tick_source <= dat_i[0];
-           tick_int_enable <= dat_i[1];
-           external_sync <= dat_i[2];
-        end
+     else if(wb_write)
+       case(adr_i[2:0])
+        3'd0 :
+          begin
+             tick_source <= dat_i[0];
+             tick_int_enable <= dat_i[1];
+             external_sync <= dat_i[2];
+          end
+        3'd1 :
+          tick_interval <= dat_i;
+        3'd2 :
+          delta_time <= dat_i;
+        3'd3 :
+          ;
+        // Do nothing here, this is to arm the sync_on_next
+       endcase // case(adr_i[2:0])
+
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       sync_on_next_pps <= 0;
+     else if(pps_ext)
+       sync_on_next_pps <= 0;
+     else if(wb_write & (adr_i[2:0] == 3))
+       sync_on_next_pps <= 0;
    
    always @(posedge sys_clk_i)
      if(internal_tick)