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[Commit-gnuradio] r9815 - gnuradio/trunk/usrp2/fpga/top/u2_rev2
From: |
matt |
Subject: |
[Commit-gnuradio] r9815 - gnuradio/trunk/usrp2/fpga/top/u2_rev2 |
Date: |
Tue, 21 Oct 2008 18:29:15 -0600 (MDT) |
Author: matt
Date: 2008-10-21 18:29:15 -0600 (Tue, 21 Oct 2008)
New Revision: 9815
Modified:
gnuradio/trunk/usrp2/fpga/top/u2_rev2/Makefile
Log:
make rev2 compile again
Modified: gnuradio/trunk/usrp2/fpga/top/u2_rev2/Makefile
===================================================================
--- gnuradio/trunk/usrp2/fpga/top/u2_rev2/Makefile 2008-10-22 00:29:10 UTC
(rev 9814)
+++ gnuradio/trunk/usrp2/fpga/top/u2_rev2/Makefile 2008-10-22 00:29:15 UTC
(rev 9815)
@@ -62,7 +62,6 @@
control_lib/dcache.v \
control_lib/decoder_3_8.v \
control_lib/dpram32.v \
-control_lib/extram_interface.v \
control_lib/fifo_2clock.v \
control_lib/fifo_2clock_casc.v \
control_lib/gray2bin.v \
@@ -89,6 +88,7 @@
control_lib/oneshot_2clk.v \
control_lib/sd_spi.v \
control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
coregen/fifo_xlnx_2Kx36_2clk.v \
coregen/fifo_xlnx_2Kx36_2clk.xco \
coregen/fifo_xlnx_512x36_2clk.v \
@@ -120,6 +120,7 @@
eth/rtl/verilog/miim/eth_clockgen.v \
eth/rtl/verilog/miim/eth_outputcontrol.v \
eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \
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