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[Commit-gnuradio] r9748 - gnuradio/branches/developers/eb/cppdb-wip/usrp
|
From: |
eb |
|
Subject: |
[Commit-gnuradio] r9748 - gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy |
|
Date: |
Wed, 8 Oct 2008 01:05:59 -0600 (MDT) |
Author: eb
Date: 2008-10-08 01:05:57 -0600 (Wed, 08 Oct 2008)
New Revision: 9748
Modified:
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.cc
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.h
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_boards.cc
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.cc
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.h
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_standard.cc
Log:
work-in-progress re-refactoring usrp_basic. lib/legacy builds. untested.
Modified:
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.cc
===================================================================
--- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.cc
2008-10-08 06:29:43 UTC (rev 9747)
+++ gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.cc
2008-10-08 07:05:57 UTC (rev 9748)
@@ -42,9 +42,6 @@
d_tx = tx;
d_usrp = usrp;
- // FIXME: this is a stupid response some the Python examples requiring _which
- _which = which;
-
if(d_tx) {
d_slot = d_which * 2;
}
@@ -299,6 +296,7 @@
throw std::runtime_error("_reflck_divisor() called from base class\n");;
}
+#if 0 // FIXME tune shouldn't be a method of db_base
tune_result
db_base::tune(int chan, double target_freq)
{
@@ -371,3 +369,5 @@
return res;
}
+#endif
+
Modified:
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.h
===================================================================
--- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.h
2008-10-08 06:29:43 UTC (rev 9747)
+++ gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.h
2008-10-08 07:05:57 UTC (rev 9748)
@@ -90,22 +90,21 @@
virtual double lo_offset();
virtual void select_rx_antenna(int which_antenna);
- tune_result tune(int chan, double target_freq);
+ // FIXME tune shouldn't be a method of db_base
+ // tune_result tune(int chan, double target_freq);
int which() { return d_which; }
- int _which;
-
protected:
void _enable_refclk(bool enable);
virtual double _refclk_freq();
virtual int _refclk_divisor();
- int d_which;
- usrp_basic *d_usrp;
- int d_refclk_reg;
- bool d_tx;
- int d_slot;
+ usrp_basic *d_usrp;
+ int d_which;
+ bool d_tx;
+ int d_refclk_reg;
+ int d_slot;
};
#endif
Modified:
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_boards.cc
===================================================================
--- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_boards.cc
2008-10-08 06:29:43 UTC (rev 9747)
+++ gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_boards.cc
2008-10-08 07:05:57 UTC (rev 9748)
@@ -58,7 +58,8 @@
break;
case(USRP_DBID_DBS_RX):
- db.push_back(db_base_sptr(new db_dbs_rx(usrp, which_side))); break;
+ db.push_back(db_base_sptr(new db_dbs_rx(usrp, which_side)));
+ break;
case(USRP_DBID_TV_RX):
db.push_back(db_base_sptr(new db_tv_rx(usrp, which_side, 43.75e6,
5.75e6)));
@@ -183,7 +184,7 @@
break;
case(-1):
- if(usrp->istx()) {
+ if (dynamic_cast<usrp_basic_tx*>(usrp)){
db.push_back(db_base_sptr(new db_basic_tx(usrp, which_side)));
}
else {
@@ -194,7 +195,7 @@
case(-2):
default:
- if(usrp->istx()) {
+ if (dynamic_cast<usrp_basic_tx*>(usrp)){
fprintf(stderr, "\n\aWarning: Treating daughterboard with invalid EEPROM
contents as if it were a \"Basic Tx.\"\n");
fprintf(stderr, "Warning: This is almost certainly wrong... Use
appropriate burn-*-eeprom utility.\n\n");
db.push_back(db_base_sptr(new db_basic_tx(usrp, which_side)));
Modified:
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.cc
===================================================================
---
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.cc
2008-10-08 06:29:43 UTC (rev 9747)
+++
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.cc
2008-10-08 07:05:57 UTC (rev 9748)
@@ -180,22 +180,22 @@
}
bool
-usrp_basic::write_aux_dac (int slot, int which_dac, int value)
+usrp_basic::_write_aux_dac (int slot, int which_dac, int value)
{
return usrp_write_aux_dac (d_udh, slot, which_dac, value);
}
bool
-usrp_basic::read_aux_adc (int slot, int which_adc, int *value)
+usrp_basic::_read_aux_adc (int slot, int which_adc, int *value)
{
return usrp_read_aux_adc (d_udh, slot, which_adc, value);
}
int
-usrp_basic::read_aux_adc (int slot, int which_adc)
+usrp_basic::_read_aux_adc (int slot, int which_adc)
{
int value;
- if (!read_aux_adc (slot, which_adc, &value))
+ if (!_read_aux_adc (slot, which_adc, &value))
return READ_FAILED;
return value;
@@ -314,6 +314,13 @@
return ok;
}
+bool
+usrp_basic::set_dc_offset_cl_enable(int bits, int mask)
+{
+ return _write_fpga_reg(FR_DC_OFFSET_CL_EN,
+ (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits &
mask));
+}
+
// ----------------------------------------------------------------
bool
@@ -418,6 +425,189 @@
return usrp_set_led (d_udh, which_led, on);
}
+/*
+ * ----------------------------------------------------------------
+ * Routines to access and control daughterboard specific i/o
+ * ----------------------------------------------------------------
+ */
+static int
+slot_id_to_oe_reg (int slot_id)
+{
+ static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };
+ assert (0 <= slot_id && slot_id < 4);
+ return reg[slot_id];
+}
+
+static int
+slot_id_to_io_reg (int slot_id)
+{
+ static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };
+ assert (0 <= slot_id && slot_id < 4);
+ return reg[slot_id];
+}
+
+static int
+to_slot(txrx_t txrx, int which_side)
+{
+ // TX_A = 0
+ // RX_A = 1
+ // TX_B = 2
+ // RX_B = 3
+ return ((which_side & 0x1) << 1) | ((txrx & 0x1) == C_RX);
+}
+
+bool
+usrp_basic::common_set_pga(txrx_t txrx, int which_amp, double gain)
+{
+ if (which_amp < 0 || which_amp > 3)
+ return false;
+
+ gain = std::min(common_pga_max(txrx),
+ std::max(common_pga_min(txrx), gain));
+
+ int codec = which_amp >> 1;
+ int int_gain = (int) rint((gain - common_pga_min(txrx)) /
common_pga_db_per_step(txrx));
+
+ if (txrx == C_TX){ // 0 and 1 are same, as are 2 and 3
+ return _write_9862(codec, REG_TX_PGA, int_gain);
+ }
+ else {
+ int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
+
+ // read current value to get input buffer bypass flag.
+ unsigned char cur_rx;
+ if (!_read_9862(codec, reg, &cur_rx))
+ return false;
+
+ cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);
+ return _write_9862(codec, reg, cur_rx);
+ }
+}
+
+double
+usrp_basic::common_pga(txrx_t txrx, int which_amp) const
+{
+ if (which_amp < 0 || which_amp > 3)
+ return READ_FAILED;
+
+ if (txrx == C_TX){
+ int codec = which_amp >> 1;
+ unsigned char v;
+ bool ok = _read_9862 (codec, REG_TX_PGA, &v);
+ if (!ok)
+ return READ_FAILED;
+
+ return (pga_db_per_step() * v) + pga_min();
+ }
+ else {
+ int codec = which_amp >> 1;
+ int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
+ unsigned char v;
+ bool ok = _read_9862 (codec, reg, &v);
+ if (!ok)
+ return READ_FAILED;
+
+ return (pga_db_per_step() * (v & 0x1f)) + pga_min();
+ }
+}
+
+double
+usrp_basic::common_pga_min(txrx_t txrx) const
+{
+ if (txrx == C_TX)
+ return -20.0;
+ else
+ return 0.0;
+}
+
+double
+usrp_basic::common_pga_max(txrx_t txrx) const
+{
+ if (txrx == C_TX)
+ return 0.0;
+ else
+ return 20.0;
+}
+
+double
+usrp_basic::common_pga_db_per_step(txrx_t txrx) const
+{
+ if (txrx == C_TX)
+ return 20.0 / 255;
+ else
+ return 20.0 / 20;
+}
+
+bool
+usrp_basic::_common_write_oe(txrx_t txrx, int which_side, int value, int mask)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ return _write_fpga_reg(slot_id_to_oe_reg(to_slot(txrx, which_side)),
+ (mask << 16) | (value & 0xffff));
+}
+
+bool
+usrp_basic::common_write_io(txrx_t txrx, int which_side, int value, int mask)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ return _write_fpga_reg(slot_id_to_io_reg(to_slot(txrx, which_side)),
+ (mask << 16) | (value & 0xffff));
+}
+
+bool
+usrp_basic::common_read_io(txrx_t txrx, int which_side, int *value)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ int t;
+ int reg = which_side + 1; // FIXME, *very* magic number (fix in
serial_io.v)
+ bool ok = _read_fpga_reg(reg, &t);
+ if (!ok)
+ return false;
+
+ if (txrx == C_TX){
+ *value = t & 0xffff; // FIXME, more magic
+ return true;
+ }
+ else {
+ *value = (t >> 16) & 0xffff; // FIXME, more magic
+ return true;
+ }
+}
+
+int
+usrp_basic::common_read_io(txrx_t txrx, int which_side)
+{
+ int value;
+ if (!common_read_io(txrx, which_side, &value))
+ return READ_FAILED;
+ return value;
+}
+
+bool
+usrp_basic::common_write_aux_dac(txrx_t txrx, int which_side, int which_dac,
int value)
+{
+ return _write_aux_dac(to_slot(txrx, which_side), which_dac, value);
+}
+
+bool
+usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc,
int *value)
+{
+ return _read_aux_adc(to_slot(txrx, which_side), which_adc, value);
+}
+
+int
+usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc)
+{
+ return _read_aux_adc(to_slot(txrx, which_side), which_adc);
+}
+
+
////////////////////////////////////////////////////////////////
//
// usrp_basic_rx
@@ -656,61 +846,6 @@
set_rx_enable (on);
}
-bool
-usrp_basic_rx::set_pga (int which_amp, double gain)
-{
- if (which_amp < 0 || which_amp > 3)
- return false;
-
- gain = std::max (pga_min (), gain);
- gain = std::min (pga_max (), gain);
-
- int codec = which_amp >> 1;
- int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
-
- // read current value to get input buffer bypass flag.
- unsigned char cur_rx;
- if (!_read_9862 (codec, reg, &cur_rx))
- return false;
-
- int int_gain = (int) rint ((gain - pga_min ()) / pga_db_per_step());
-
- cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);
- return _write_9862 (codec, reg, cur_rx);
-}
-
-double
-usrp_basic_rx::pga (int which_amp) const
-{
- if (which_amp < 0 || which_amp > 3)
- return READ_FAILED;
-
- int codec = which_amp >> 1;
- int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
- unsigned char v;
- bool ok = _read_9862 (codec, reg, &v);
- if (!ok)
- return READ_FAILED;
-
- return (pga_db_per_step() * (v & 0x1f)) + pga_min();
-}
-
-static int
-slot_id_to_oe_reg (int slot_id)
-{
- static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };
- assert (0 <= slot_id && slot_id < 4);
- return reg[slot_id];
-}
-
-static int
-slot_id_to_io_reg (int slot_id)
-{
- static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };
- assert (0 <= slot_id && slot_id < 4);
- return reg[slot_id];
-}
-
void
usrp_basic_rx::probe_rx_slots (bool verbose)
{
@@ -760,80 +895,62 @@
}
bool
-usrp_basic_rx::_write_oe (int which_side, int value, int mask)
+usrp_basic_rx::set_pga (int which_amp, double gain)
{
- if (! (0 <= which_side && which_side <= 1))
- return false;
+ return common_set_pga(C_RX, which_amp, gain);
+}
- return _write_fpga_reg (slot_id_to_oe_reg (dboard_to_slot (which_side)),
- (mask << 16) | (value & 0xffff));
+double
+usrp_basic_rx::pga (int which_amp) const
+{
+ return common_pga(C_RX, which_amp);
}
bool
+usrp_basic_rx::_write_oe (int which_side, int value, int mask)
+{
+ return _common_write_oe(C_RX, which_side, value, mask);
+}
+
+bool
usrp_basic_rx::write_io (int which_side, int value, int mask)
{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- return _write_fpga_reg (slot_id_to_io_reg (dboard_to_slot (which_side)),
- (mask << 16) | (value & 0xffff));
+ return common_write_io(C_RX, which_side, value, mask);
}
bool
usrp_basic_rx::read_io (int which_side, int *value)
{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- int t;
- int reg = which_side + 1; // FIXME, *very* magic number (fix in
serial_io.v)
- bool ok = _read_fpga_reg (reg, &t);
- if (!ok)
- return false;
-
- *value = (t >> 16) & 0xffff; // FIXME, more magic
- return true;
+ return common_read_io(C_RX, which_side, value);
}
int
usrp_basic_rx::read_io (int which_side)
{
- int value;
- if (!read_io (which_side, &value))
- return READ_FAILED;
- return value;
+ return common_read_io(C_RX, which_side);
}
bool
usrp_basic_rx::write_aux_dac (int which_side, int which_dac, int value)
{
- return usrp_basic::write_aux_dac (dboard_to_slot (which_side),
- which_dac, value);
+ return common_write_aux_dac(C_RX, which_side, which_dac, value);
}
bool
usrp_basic_rx::read_aux_adc (int which_side, int which_adc, int *value)
{
- return usrp_basic::read_aux_adc (dboard_to_slot (which_side),
- which_adc, value);
+ return common_read_aux_adc(C_RX, which_side, which_adc, value);
}
int
usrp_basic_rx::read_aux_adc (int which_side, int which_adc)
{
- return usrp_basic::read_aux_adc (dboard_to_slot (which_side), which_adc);
+ return common_read_aux_adc(C_RX, which_side, which_adc);
}
int
usrp_basic_rx::block_size () const { return d_ephandle->block_size(); }
-bool
-usrp_basic_rx::set_dc_offset_cl_enable(int bits, int mask)
-{
- return _write_fpga_reg(FR_DC_OFFSET_CL_EN,
- (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits &
mask));
-}
-
////////////////////////////////////////////////////////////////
//
// usrp_basic_tx
@@ -1094,37 +1211,6 @@
set_tx_enable (on);
}
-bool
-usrp_basic_tx::set_pga (int which_amp, double gain)
-{
- if (which_amp < 0 || which_amp > 3)
- return false;
-
- gain = std::max (pga_min (), gain);
- gain = std::min (pga_max (), gain);
-
- int codec = which_amp >> 1; // 0 and 1 are same, as are 2 and 3
-
- int int_gain = (int) rint ((gain - pga_min ()) / pga_db_per_step());
-
- return _write_9862 (codec, REG_TX_PGA, int_gain);
-}
-
-double
-usrp_basic_tx::pga (int which_amp) const
-{
- if (which_amp < 0 || which_amp > 3)
- return READ_FAILED;
-
- int codec = which_amp >> 1;
- unsigned char v;
- bool ok = _read_9862 (codec, REG_TX_PGA, &v);
- if (!ok)
- return READ_FAILED;
-
- return (pga_db_per_step() * v) + pga_min();
-}
-
void
usrp_basic_tx::probe_tx_slots (bool verbose)
{
@@ -1174,68 +1260,57 @@
}
bool
-usrp_basic_tx::_write_oe (int which_side, int value, int mask)
+usrp_basic_tx::set_pga (int which_amp, double gain)
{
- if (! (0 <= which_side && which_side <= 1))
- return false;
+ return common_set_pga(C_TX, which_amp, gain);
+}
- return _write_fpga_reg (slot_id_to_oe_reg (dboard_to_slot (which_side)),
- (mask << 16) | (value & 0xffff));
+double
+usrp_basic_tx::pga (int which_amp) const
+{
+ return common_pga(C_TX, which_amp);
}
bool
+usrp_basic_tx::_write_oe (int which_side, int value, int mask)
+{
+ return _common_write_oe(C_TX, which_side, value, mask);
+}
+
+bool
usrp_basic_tx::write_io (int which_side, int value, int mask)
{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- return _write_fpga_reg (slot_id_to_io_reg (dboard_to_slot (which_side)),
- (mask << 16) | (value & 0xffff));
+ return common_write_io(C_TX, which_side, value, mask);
}
bool
usrp_basic_tx::read_io (int which_side, int *value)
{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- int t;
- int reg = which_side + 1; // FIXME, *very* magic number (fix in
serial_io.v)
- bool ok = _read_fpga_reg (reg, &t);
- if (!ok)
- return false;
-
- *value = t & 0xffff; // FIXME, more magic
- return true;
+ return common_read_io(C_TX, which_side, value);
}
int
usrp_basic_tx::read_io (int which_side)
{
- int value;
- if (!read_io (which_side, &value))
- return READ_FAILED;
- return value;
+ return common_read_io(C_TX, which_side);
}
bool
usrp_basic_tx::write_aux_dac (int which_side, int which_dac, int value)
{
- return usrp_basic::write_aux_dac (dboard_to_slot (which_side),
- which_dac, value);
+ return common_write_aux_dac(C_TX, which_side, which_dac, value);
}
bool
usrp_basic_tx::read_aux_adc (int which_side, int which_adc, int *value)
{
- return usrp_basic::read_aux_adc (dboard_to_slot (which_side),
- which_adc, value);
+ return common_read_aux_adc(C_TX, which_side, which_adc, value);
}
int
usrp_basic_tx::read_aux_adc (int which_side, int which_adc)
{
- return usrp_basic::read_aux_adc (dboard_to_slot (which_side), which_adc);
+ return common_read_aux_adc(C_TX, which_side, which_adc);
}
int
Modified:
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.h
===================================================================
--- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.h
2008-10-08 06:29:43 UTC (rev 9747)
+++ gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.h
2008-10-08 07:05:57 UTC (rev 9748)
@@ -41,22 +41,29 @@
#include <usrp_slots.h>
#include <string>
+#include <boost/shared_ptr.hpp>
+#include <boost/utility.hpp>
+
+class db_base;
+typedef boost::shared_ptr<db_base> db_base_sptr;
+
+
struct usb_dev_handle;
class fusb_devhandle;
class fusb_ephandle;
+enum txrx_t {
+ C_RX = 0,
+ C_TX = 1
+};
+
+
/*!
* \brief base class for usrp operations
*/
-class usrp_basic
+class usrp_basic : boost::noncopyable
{
-private:
- // NOT IMPLEMENTED
- usrp_basic (const usrp_basic &rhs); // no copy constructor
- usrp_basic &operator= (const usrp_basic &rhs); // no assignment
operator
-
-
protected:
struct usb_dev_handle *d_udh;
int d_usb_data_rate; // bytes/sec
@@ -92,7 +99,7 @@
* \param value [0,4095]
* \returns true iff successful
*/
- bool write_aux_dac (int slot, int which_dac, int value);
+ bool _write_aux_dac (int slot, int which_dac, int value);
/*!
* \brief Read auxiliary analog to digital converter.
@@ -102,7 +109,7 @@
* \param value return 12-bit value [0,4095]
* \returns true iff successful
*/
- bool read_aux_adc (int slot, int which_adc, int *value);
+ bool _read_aux_adc (int slot, int which_adc, int *value);
/*!
* \brief Read auxiliary analog to digital converter.
@@ -111,8 +118,9 @@
* \param which_adc [0,1]
* \returns value in the range [0,4095] if successful, else READ_FAILED.
*/
- int read_aux_adc (int slot, int which_adc);
+ int _read_aux_adc (int slot, int which_adc);
+
public:
virtual ~usrp_basic ();
@@ -191,6 +199,27 @@
*/
bool set_adc_buffer_bypass (int which_adc, bool bypass);
+ /*!
+ * \brief Enable/disable automatic DC offset removal control loop in FPGA
+ *
+ * \param bits which control loops to enable
+ * \param mask which \p bits to pay attention to
+ *
+ * If the corresponding bit is set, enable the automatic DC
+ * offset correction control loop.
+ *
+ * <pre>
+ * The 4 low bits are significant:
+ *
+ * ADC0 = (1 << 0)
+ * ADC1 = (1 << 1)
+ * ADC2 = (1 << 2)
+ * ADC3 = (1 << 3)
+ * </pre>
+ *
+ * By default the control loop is enabled on all ADC's.
+ */
+ bool set_dc_offset_cl_enable(int bits, int mask);
/*!
* \brief return the usrp's serial number.
@@ -199,7 +228,277 @@
*/
std::string serial_number();
+ /*!
+ * \brief Return daughterboard ID for given side [0,1].
+ *
+ * \param which_side [0,1] which daughterboard
+ *
+ * \return daughterboard id >= 0 if successful
+ * \return -1 if no daugherboard
+ * \return -2 if invalid EEPROM on daughterboard
+ */
+ virtual int daughterboard_id (int which_side) const = 0;
+
+ // ================================================================
+ // Routines to access and control daughterboard specific i/o
+ //
+ // Those with a common_ prefix access either the Tx or Rx side depending
+ // on the txrx parameter. Those without the common_ prefix are virtual
+ // and are overriden in usrp_basic_rx and usrp_basic_tx to access the
+ // the Rx or Tx sides automatically. We provide the common_ versions
+ // for those daughterboards such as the WBX and XCVR2450 that share
+ // h/w resources (such as the LO) between the Tx and Rx sides.
+
// ----------------------------------------------------------------
+ // BEGIN common_ daughterboard control functions
+
+ /*!
+ * \brief Set Programmable Gain Amplifier(PGA)
+ *
+ * \param txrx Tx or Rx?
+ * \param which_amp which amp [0,3]
+ * \param gain_in_db gain value(linear in dB)
+ *
+ * gain is rounded to closest setting supported by hardware.
+ *
+ * \returns true iff sucessful.
+ *
+ * \sa pga_min(), pga_max(), pga_db_per_step()
+ */
+ bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
+
+ /*!
+ * \brief Return programmable gain amplifier gain setting in dB.
+ *
+ * \param txrx Tx or Rx?
+ * \param which_amp which amp [0,3]
+ */
+ double common_pga(txrx_t txrx, int which_amp) const;
+
+ /*!
+ * \brief Return minimum legal PGA gain in dB.
+ * \param txrx Tx or Rx?
+ */
+ double common_pga_min(txrx_t txrx) const;
+
+ /*!
+ * \brief Return maximum legal PGA gain in dB.
+ * \param txrx Tx or Rx?
+ */
+ double common_pga_max(txrx_t txrx) const;
+
+ /*!
+ * \brief Return hardware step size of PGA(linear in dB).
+ * \param txrx Tx or Rx?
+ */
+ double common_pga_db_per_step(txrx_t txrx) const;
+
+ /*!
+ * \brief Write direction register(output enables) for pins that go to
daughterboard.
+ *
+ * \param txrx Tx or Rx?
+ * \param which_side [0,1] which size
+ * \param value value to write into register
+ * \param mask which bits of value to write into reg
+ *
+ * Each d'board has 16-bits of general purpose i/o.
+ * Setting the bit makes it an output from the FPGA to the d'board.
+ *
+ * This register is initialized based on a value stored in the
+ * d'board EEPROM. In general, you shouldn't be using this routine
+ * without a very good reason. Using this method incorrectly will
+ * kill your USRP motherboard and/or daughterboard.
+ */
+ bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
+
+ /*!
+ * \brief Write daughterboard i/o pin value
+ *
+ * \param txrx Tx or Rx?
+ * \param which_side [0,1] which d'board
+ * \param value value to write into register
+ * \param mask which bits of value to write into reg
+ */
+ bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
+
+ /*!
+ * \brief Read daughterboard i/o pin value
+ *
+ * \param txrx Tx or Rx?
+ * \param which_side [0,1] which d'board
+ * \param value output
+ */
+ bool common_read_io(txrx_t txrx, int which_side, int *value);
+
+ /*!
+ * \brief Read daughterboard i/o pin value
+ *
+ * \param txrx Tx or Rx?
+ * \param which_side [0,1] which d'board
+ * \returns register value if successful, else READ_FAILED
+ */
+ int common_read_io(txrx_t txrx, int which_side);
+
+ /*!
+ * \brief Write auxiliary digital to analog converter.
+ *
+ * \param txrx Tx or Rx?
+ * \param which_side [0,1] which d'board
+ * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
+ * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
+ * \param which_dac [2,3] TX slots must use only 2 and 3.
+ * \param value [0,4095]
+ * \returns true iff successful
+ */
+ bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int
value);
+
+ /*!
+ * \brief Read auxiliary analog to digital converter.
+ *
+ * \param txrx Tx or Rx?
+ * \param which_side [0,1] which d'board
+ * \param which_adc [0,1]
+ * \param value return 12-bit value [0,4095]
+ * \returns true iff successful
+ */
+ bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int
*value);
+
+ /*!
+ * \brief Read auxiliary analog to digital converter.
+ *
+ * \param txrx Tx or Rx?
+ * \param which_side [0,1] which d'board
+ * \param which_adc [0,1]
+ * \returns value in the range [0,4095] if successful, else READ_FAILED.
+ */
+ int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
+
+ // END common_ daughterboard control functions
+ // ----------------------------------------------------------------
+ // BEGIN virtual daughterboard control functions
+
+ /*!
+ * \brief Set Programmable Gain Amplifier (PGA)
+ *
+ * \param which_amp which amp [0,3]
+ * \param gain_in_db gain value (linear in dB)
+ *
+ * gain is rounded to closest setting supported by hardware.
+ *
+ * \returns true iff sucessful.
+ *
+ * \sa pga_min(), pga_max(), pga_db_per_step()
+ */
+ virtual bool set_pga (int which_amp, double gain_in_db) = 0;
+
+ /*!
+ * \brief Return programmable gain amplifier gain setting in dB.
+ *
+ * \param which_amp which amp [0,3]
+ */
+ virtual double pga (int which_amp) const = 0;
+
+ /*!
+ * \brief Return minimum legal PGA gain in dB.
+ */
+ virtual double pga_min () const = 0;
+
+ /*!
+ * \brief Return maximum legal PGA gain in dB.
+ */
+ virtual double pga_max () const = 0;
+
+ /*!
+ * \brief Return hardware step size of PGA (linear in dB).
+ */
+ virtual double pga_db_per_step () const = 0;
+
+ /*!
+ * \brief Write direction register (output enables) for pins that go to
daughterboard.
+ *
+ * \param which_side [0,1] which size
+ * \param value value to write into register
+ * \param mask which bits of value to write into reg
+ *
+ * Each d'board has 16-bits of general purpose i/o.
+ * Setting the bit makes it an output from the FPGA to the d'board.
+ *
+ * This register is initialized based on a value stored in the
+ * d'board EEPROM. In general, you shouldn't be using this routine
+ * without a very good reason. Using this method incorrectly will
+ * kill your USRP motherboard and/or daughterboard.
+ */
+ virtual bool _write_oe (int which_side, int value, int mask) = 0;
+
+ /*!
+ * \brief Write daughterboard i/o pin value
+ *
+ * \param which_side [0,1] which d'board
+ * \param value value to write into register
+ * \param mask which bits of value to write into reg
+ */
+ virtual bool write_io (int which_side, int value, int mask) = 0;
+
+ /*!
+ * \brief Read daughterboard i/o pin value
+ *
+ * \param which_side [0,1] which d'board
+ * \param value output
+ */
+ virtual bool read_io (int which_side, int *value) = 0;
+
+ /*!
+ * \brief Read daughterboard i/o pin value
+ *
+ * \param which_side [0,1] which d'board
+ * \returns register value if successful, else READ_FAILED
+ */
+ virtual int read_io (int which_side) = 0;
+
+ /*!
+ * \brief Write auxiliary digital to analog converter.
+ *
+ * \param which_side [0,1] which d'board
+ * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
+ * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
+ * \param which_dac [2,3] TX slots must use only 2 and 3.
+ * \param value [0,4095]
+ * \returns true iff successful
+ */
+ virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
+
+ /*!
+ * \brief Read auxiliary analog to digital converter.
+ *
+ * \param which_side [0,1] which d'board
+ * \param which_adc [0,1]
+ * \param value return 12-bit value [0,4095]
+ * \returns true iff successful
+ */
+ virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
+
+ /*!
+ * \brief Read auxiliary analog to digital converter.
+ *
+ * \param which_side [0,1] which d'board
+ * \param which_adc [0,1]
+ * \returns value in the range [0,4095] if successful, else READ_FAILED.
+ */
+ virtual int read_aux_adc (int which_side, int which_adc) = 0;
+
+ /*!
+ * \brief returns current fusb block size
+ */
+ virtual int block_size() const = 0;
+
+ /*!
+ * \brief returns A/D or D/A converter rate in Hz
+ */
+ virtual long converter_rate() const = 0;
+
+ // END virtual daughterboard control functions
+
+ // ----------------------------------------------------------------
// Low level implementation routines.
// You probably shouldn't be using these...
//
@@ -229,7 +528,6 @@
*/
int _read_fpga_reg (int regno);
-
/*!
* \brief Write FPGA register with mask.
* \param regno 7-bit register number
@@ -346,7 +644,6 @@
void restore_rx (bool on); // conditional set
void probe_rx_slots (bool verbose);
- int dboard_to_slot (int dboard) { return (dboard << 1) | 1; }
public:
~usrp_basic_rx ();
@@ -358,6 +655,8 @@
* \param fusb_block_size fast usb xfer block size. Must be a multiple of
512.
* Use zero for a reasonable default.
* \param fusb_nblocks number of fast usb URBs to allocate. Use zero
for a reasonable default.
+ * \param fpga_filename name of file that contains image to load into FPGA
+ * \param firmware_filename name of file that contains image to load into
FX2
*/
static usrp_basic_rx *make (int which_board,
int fusb_block_size=0,
@@ -366,8 +665,6 @@
const std::string firmware_filename = ""
);
- // MANIPULATORS
-
/*!
* \brief tell the fpga the rate rx samples are coming from the A/D's
*
@@ -389,162 +686,29 @@
*/
int read (void *buf, int len, bool *overrun);
- // ACCESSORS
//! sampling rate of A/D converter
virtual long converter_rate() const { return fpga_master_clock_freq(); } //
64M
long adc_rate() const { return converter_rate(); }
- long adc_freq() const { return converter_rate(); } //!< deprecated method
name
-
- /*!
- * \brief Return daughterboard ID for given Rx daughterboard slot [0,1].
- *
- * \param which_side [0,1] which Rx daughterboard
- *
- * \return daughterboard id >= 0 if successful
- * \return -1 if no daugherboard
- * \return -2 if invalid EEPROM on daughterboard
- */
int daughterboard_id (int which_side) const { return d_dbid[which_side &
0x1]; }
- // ----------------------------------------------------------------
- // routines for controlling the Programmable Gain Amplifier
- /*!
- * \brief Set Programmable Gain Amplifier (PGA)
- *
- * \param which_amp which A/D [0,3]
- * \param gain_in_db gain value (linear in dB)
- *
- * gain is rounded to closest setting supported by hardware.
- *
- * \returns true iff sucessful.
- *
- * \sa pga_min(), pga_max(), pga_db_per_step()
- */
bool set_pga (int which_amp, double gain_in_db);
-
- /*!
- * \brief Return programmable gain amplifier gain setting in dB.
- *
- * \param which_amp which A/D [0,3]
- */
double pga (int which_amp) const;
+ double pga_min () const;
+ double pga_max () const;
+ double pga_db_per_step () const;
- /*!
- * \brief Return minimum legal PGA gain in dB.
- */
- double pga_min () const { return 0.0; }
-
- /*!
- * \brief Return maximum legal PGA gain in dB.
- */
- double pga_max () const { return 20.0; }
-
- /*!
- * \brief Return hardware step size of PGA (linear in dB).
- */
- double pga_db_per_step () const { return 20.0 / 20; }
-
- /*!
- * \brief Write direction register (output enables) for pins that go to
daughterboard.
- *
- * \param which_side [0,1] which d'board
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- *
- * Each d'board has 16-bits of general purpose i/o.
- * Setting the bit makes it an output from the FPGA to the d'board.
- *
- * This register is initialized based on a value stored in the
- * d'board EEPROM. In general, you shouldn't be using this routine
- * without a very good reason. Using this method incorrectly will
- * kill your USRP motherboard and/or daughterboard.
- */
bool _write_oe (int which_side, int value, int mask);
-
- /*!
- * \brief Write daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- */
bool write_io (int which_side, int value, int mask);
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \param value output
- */
bool read_io (int which_side, int *value);
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \returns register value if successful, else READ_FAILED
- */
int read_io (int which_side);
- /*!
- * \brief Write auxiliary digital to analog converter.
- *
- * \param which_side [0,1] which d'board
- * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
- * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
- * \param which_dac [2,3] TX slots must use only 2 and 3.
- * \param value [0,4095]
- * \returns true iff successful
- */
bool write_aux_dac (int which_side, int which_dac, int value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \param value return 12-bit value [0,4095]
- * \returns true iff successful
- */
bool read_aux_adc (int which_side, int which_adc, int *value);
+ int read_aux_adc (int which_side, int which_adc);
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \returns value in the range [0,4095] if successful, else READ_FAILED.
- */
- int read_aux_adc (int which_side, int which_adc);
-
- /*!
- * \brief returns current fusb block size
- */
int block_size() const;
- /*!
- * \brief Enable/disable automatic DC offset removal control loop in FPGA
- *
- * \param bits which control loops to enable
- * \param mask which \p bits to pay attention to
- *
- * If the corresponding bit is set, enable the automatic DC
- * offset correction control loop.
- *
- * <pre>
- * The 4 low bits are significant:
- *
- * ADC0 = (1 << 0)
- * ADC1 = (1 << 1)
- * ADC2 = (1 << 2)
- * ADC3 = (1 << 3)
- * </pre>
- *
- * By default the control loop is enabled on all ADC's.
- */
- bool set_dc_offset_cl_enable(int bits, int mask);
-
// called in base class to derived class order
bool start ();
bool stop ();
@@ -570,6 +734,8 @@
* \param fusb_block_size fast usb xfer block size. Must be a multiple of
512.
* Use zero for a reasonable default.
* \param fusb_nblocks number of fast usb URBs to allocate. Use zero
for a reasonable default.
+ * \param fpga_filename name of file that contains image to load into FPGA
+ * \param firmware_filename name of file that contains image to load into
FX2
*/
usrp_basic_tx (int which_board,
int fusb_block_size=0,
@@ -585,7 +751,6 @@
void restore_tx (bool on); // conditional set
void probe_tx_slots (bool verbose);
- int dboard_to_slot (int dboard) { return (dboard << 1) | 0; }
public:
@@ -598,14 +763,14 @@
* \param fusb_block_size fast usb xfer block size. Must be a multiple of
512.
* Use zero for a reasonable default.
* \param fusb_nblocks number of fast usb URBs to allocate. Use zero
for a reasonable default.
+ * \param fpga_filename name of file that contains image to load into FPGA
+ * \param firmware_filename name of file that contains image to load into
FX2
*/
static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int
fusb_nblocks=0,
const std::string fpga_filename = "",
const std::string firmware_filename = ""
);
- // MANIPULATORS
-
/*!
* \brief tell the fpga the rate tx samples are going to the D/A's
*
@@ -634,138 +799,26 @@
*/
void wait_for_completion ();
- // ACCESSORS
-
//! sampling rate of D/A converter
virtual long converter_rate() const { return fpga_master_clock_freq () * 2;
} // 128M
long dac_rate() const { return converter_rate(); }
- long dac_freq() const { return converter_rate(); } //!< deprecated method
name
-
- /*!
- * \brief Return daughterboard ID for given Tx daughterboard slot [0,1].
- *
- * \return daughterboard id >= 0 if successful
- * \return -1 if no daugherboard
- * \return -2 if invalid EEPROM on daughterboard
- */
int daughterboard_id (int which_side) const { return d_dbid[which_side &
0x1]; }
- // ----------------------------------------------------------------
- // routines for controlling the Programmable Gain Amplifier
- /*!
- * \brief Set Programmable Gain Amplifier (PGA)
- *
- * \param which_amp which D/A [0,3]
- * \param gain_in_db gain value (linear in dB)
- *
- * gain is rounded to closest setting supported by hardware.
- * Note that DAC 0 and DAC 1 share a gain setting as do DAC 2 and DAC 3.
- * Setting DAC 0 affects DAC 1 and vice versa. Same with DAC 2 and DAC 3.
- *
- * \returns true iff sucessful.
- *
- * \sa pga_min(), pga_max(), pga_db_per_step()
- */
bool set_pga (int which_amp, double gain_in_db);
-
- /*!
- * \brief Return programmable gain amplifier gain in dB.
- *
- * \param which_amp which D/A [0,3]
- */
double pga (int which_amp) const;
+ double pga_min () const;
+ double pga_max () const;
+ double pga_db_per_step () const;
- /*!
- * \brief Return minimum legal PGA gain in dB.
- */
- double pga_min () const { return -20.0; }
-
- /*!
- * \brief Return maximum legal PGA gain in dB.
- */
- double pga_max () const { return 0.0; }
-
- /*!
- * \brief Return hardware step size of PGA (linear in dB).
- */
- double pga_db_per_step () const { return 20.0/255; }
-
- /*!
- * \brief Write direction register (output enables) for pins that go to
daughterboard.
- *
- * \param which_side [0,1] which d'board
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- *
- * Each d'board has 16-bits of general purpose i/o.
- * Setting the bit makes it an output from the FPGA to the d'board.
- *
- * This register is initialized based on a value stored in the
- * d'board EEPROM. In general, you shouldn't be using this routine
- * without a very good reason. Using this method incorrectly will
- * kill your USRP motherboard and/or daughterboard.
- */
bool _write_oe (int which_side, int value, int mask);
-
- /*!
- * \brief Write daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \param value value to write into register
- * \param mask which bits of value to write into reg
- */
bool write_io (int which_side, int value, int mask);
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \param value return value
- */
bool read_io (int which_side, int *value);
-
- /*!
- * \brief Read daughterboard i/o pin value
- *
- * \param which_side [0,1] which d'board
- * \returns register value if successful, else READ_FAILED
- */
int read_io (int which_side);
- /*!
- * \brief Write auxiliary digital to analog converter.
- *
- * \param which_side [0,1] which d'board
- * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
- * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
- * \param which_dac [2,3] TX slots must use only 2 and 3.
- * \param value [0,4095]
- * \returns true iff successful
- */
bool write_aux_dac (int which_side, int which_dac, int value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \param value return 12-bit value [0,4095]
- * \returns true iff successful
- */
bool read_aux_adc (int which_side, int which_adc, int *value);
-
- /*!
- * \brief Read auxiliary analog to digital converter.
- *
- * \param which_side [0,1] which d'board
- * \param which_adc [0,1]
- * \returns value in the range [0,4095] if successful, else READ_FAILED.
- */
int read_aux_adc (int which_side, int which_adc);
- /*!
- * \brief returns current fusb block size
- */
int block_size() const;
// called in base class to derived class order
Modified:
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_standard.cc
===================================================================
---
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_standard.cc
2008-10-08 06:29:43 UTC (rev 9747)
+++
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_standard.cc
2008-10-08 07:05:57 UTC (rev 9748)
@@ -379,7 +379,7 @@
return false;
unsigned int v =
- compute_freq_control_word_fpga (adc_freq(),
+ compute_freq_control_word_fpga (adc_rate(),
freq, &d_rx_freq[channel],
d_verbose);
@@ -679,7 +679,7 @@
// This assumes we're running the 4x on-chip interpolator.
unsigned int v =
- compute_freq_control_word_fpga (dac_freq () / 4,
+ compute_freq_control_word_fpga (dac_rate () / 4,
freq, &d_tx_freq[channel],
d_verbose);
@@ -700,17 +700,17 @@
coarse_mod_t cm;
double coarse;
- assert (dac_freq () == 128000000);
+ assert (dac_rate () == 128000000);
if (freq < -44e6) // too low
return false;
else if (freq < -24e6){ // [-44, -24)
cm = CM_NEG_FDAC_OVER_4;
- coarse = -dac_freq () / 4;
+ coarse = -dac_rate () / 4;
}
else if (freq < -8e6){ // [-24, -8)
cm = CM_NEG_FDAC_OVER_8;
- coarse = -dac_freq () / 8;
+ coarse = -dac_rate () / 8;
}
else if (freq < 8e6){ // [-8, 8)
cm = CM_OFF;
@@ -718,11 +718,11 @@
}
else if (freq < 24e6){ // [8, 24)
cm = CM_POS_FDAC_OVER_8;
- coarse = dac_freq () / 8;
+ coarse = dac_rate () / 8;
}
else if (freq <= 44e6){ // [24, 44]
cm = CM_POS_FDAC_OVER_4;
- coarse = dac_freq () / 4;
+ coarse = dac_rate () / 4;
}
else // too high
return false;
@@ -738,7 +738,7 @@
// (This is required to use the fine modulator.)
unsigned int v =
- compute_freq_control_word_9862 (dac_freq () / 4,
+ compute_freq_control_word_9862 (dac_rate () / 4,
fine, &d_tx_freq[channel], d_verbose);
d_tx_freq[channel] += coarse; // adjust actual
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