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[Commit-gnuradio] r7493 - usrp2/trunk/fpga/sdr_lib
From: |
matt |
Subject: |
[Commit-gnuradio] r7493 - usrp2/trunk/fpga/sdr_lib |
Date: |
Tue, 22 Jan 2008 16:06:47 -0700 (MST) |
Author: matt
Date: 2008-01-22 16:06:46 -0700 (Tue, 22 Jan 2008)
New Revision: 7493
Added:
usrp2/trunk/fpga/sdr_lib/halfband_ideal.v
usrp2/trunk/fpga/sdr_lib/halfband_tb.v
Log:
testbench courtesy of Brian Padalino
Added: usrp2/trunk/fpga/sdr_lib/halfband_ideal.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/halfband_ideal.v (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/halfband_ideal.v 2008-01-22 23:06:46 UTC (rev
7493)
@@ -0,0 +1,84 @@
+module halfband_ideal (
+ input clock,
+ input reset,
+ input enable,
+ input strobe_in,
+ input wire signed [17:0] data_in,
+ output reg strobe_out,
+ output reg signed [17:0] data_out
+) ;
+
+ parameter decim = 1 ;
+ parameter rate = 2 ;
+
+ reg signed [40:0] temp ;
+ reg signed [17:0] delay[30:0] ;
+ reg signed [17:0] coeffs[30:0] ;
+ reg [7:0] count ;
+ integer i ;
+
+ initial begin
+ for( i = 0 ; i < 31 ; i = i + 1 ) begin
+ coeffs[i] = 18'd0 ;
+ end
+ coeffs[0] = -1390 ;
+ coeffs[2] = 1604 ;
+ coeffs[4] = -1896 ;
+ coeffs[6] = 2317 ;
+ coeffs[8] = -2979 ;
+ coeffs[10] = 4172 ;
+ coeffs[12] = -6953 ;
+ coeffs[14] = 20860 ;
+ coeffs[15] = 32768 ;
+ coeffs[16] = 20860 ;
+ coeffs[18] = -6953 ;
+ coeffs[20] = 4172 ;
+ coeffs[22] = -2979 ;
+ coeffs[24] = 2317 ;
+ coeffs[26] = -1896 ;
+ coeffs[28] = 1604 ;
+ coeffs[30] = -1390 ;
+ end
+
+ always @(posedge clock) begin
+ if( reset ) begin
+ count <= 0 ;
+ for( i = 0 ; i < 31 ; i = i + 1 ) begin
+ delay[i] <= 18'd0 ;
+ end
+ temp <= 41'd0 ;
+ data_out <= 18'd0 ;
+ strobe_out <= 1'b0 ;
+ end else if( enable ) begin
+
+ if( (decim && (count == rate-1)) || !decim )
+ strobe_out <= strobe_in ;
+ else
+ strobe_out <= 1'b0 ;
+
+
+ if( strobe_in ) begin
+ // Increment decimation count
+ count <= count + 1 ;
+
+ // Shift the input
+ for( i = 30 ; i > 0 ; i = i - 1 ) begin
+ delay[i] = delay[i-1] ;
+ end
+ delay[0] = data_in ;
+
+ // clear the temp reg
+ temp = 18'd0 ;
+ if( (decim && (count == rate-1)) || !decim ) begin
+ count <= 0 ;
+ for( i = 0 ; i < 31 ; i = i + 1 ) begin
+ // Multiply Accumulate
+ temp = temp + delay[i]*coeffs[i] ;
+ end
+ // Assign data output
+ data_out <= temp >>> 15 ;
+ end
+ end
+ end
+ end
+endmodule
Added: usrp2/trunk/fpga/sdr_lib/halfband_tb.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/halfband_tb.v (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/halfband_tb.v 2008-01-22 23:06:46 UTC (rev
7493)
@@ -0,0 +1,120 @@
+module halfband_tb( ) ;
+
+ // Parameters for instantiation
+ parameter clocks = 2 ; // Number of clocks per input
+ parameter decim = 0 ; // Sets the filter to decimate
+ parameter rate = 2 ; // Sets the decimation rate
+
+ reg clock ;
+ reg reset ;
+ reg enable ;
+ reg strobe_in ;
+ reg signed [17:0] data_in ;
+ wire strobe_out ;
+ wire signed [17:0] data_out ;
+
+ // Setup the clock
+ initial clock = 1'b0 ;
+ always #5 clock <= ~clock ;
+
+ // Come out of reset after a while
+ initial reset = 1'b1 ;
+ initial #100 reset = 1'b0 ;
+
+ // Enable the entire system
+ initial enable = 1'b1 ;
+
+ // Instantiate UUT
+ halfband_ideal
+ #(
+ .decim ( decim ),
+ .rate ( rate )
+ ) uut(
+ .clock ( clock ),
+ .reset ( reset ),
+ .enable ( enable ),
+ .strobe_in ( strobe_in ),
+ .data_in ( data_in ),
+ .strobe_out ( strobe_out ),
+ .data_out ( data_out )
+ ) ;
+
+ integer i, ri, ro, infile, outfile ;
+
+ // Setup file IO
+ initial begin
+ infile = $fopen("input.dat","r") ;
+ outfile = $fopen("output.dat","r") ;
+ $timeformat(-9, 2, " ns", 10) ;
+ end
+
+ reg endofsim ;
+ reg signed [17:0] compare ;
+ integer noe ;
+ initial noe = 0 ;
+
+ initial begin
+ // Initialize inputs
+ strobe_in <= 1'd0 ;
+ data_in <= 18'd0 ;
+
+ // Wait for reset to go away
+ @(negedge reset) #0 ;
+
+ // While we're still simulating ...
+ while( !endofsim ) begin
+
+ // Write the input from the file or 0 if EOF...
+ @( posedge clock ) begin
+ #1 ;
+ strobe_in <= 1'b1 ;
+ if( !$feof(infile) )
+ ri = $fscanf( infile, "%d", data_in ) ;
+ else
+ data_in <= 18'd0 ;
+ end
+
+ // Clocked in - set the strobe to 0 if the number of
+ // clocks per sample is greater than 1
+ if( clocks > 1 ) begin
+ @(posedge clock) begin
+ strobe_in <= 1'b0 ;
+ end
+
+ // Wait for the specified number of cycles
+ for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
+ @(posedge clock) #1 ;
+ end
+ end
+ end
+
+ // Print out the number of errors that occured
+ if( noe )
+ $display( "FAILED: %d errors during simulation", noe ) ;
+ else
+ $display( "PASSED: Simulation successful" ) ;
+
+ $stop ;
+ end
+
+ // Output comparison of simulated values versus known good values
+ always @ (posedge clock) begin
+ if( reset )
+ endofsim <= 1'b0 ;
+ else begin
+ if( !$feof(outfile) ) begin
+ if( strobe_out ) begin
+ ro = $fscanf( outfile, "%d\n", compare ) ;
+ if( compare != data_out ) begin
+ $display( "%t: %d != %d", $realtime, data_out, compare
) ;
+ noe = noe + 1 ;
+ end
+ end
+ end else begin
+ // Signal end of simulation when no more outputs
+ endofsim <= 1'b1 ;
+ end
+ end
+ end
+
+endmodule
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