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[Commit-gnuradio] r7411 - usrp2/trunk/fpga/eth
From: |
matt |
Subject: |
[Commit-gnuradio] r7411 - usrp2/trunk/fpga/eth |
Date: |
Sat, 12 Jan 2008 20:57:47 -0700 (MST) |
Author: matt
Date: 2008-01-12 20:57:47 -0700 (Sat, 12 Jan 2008)
New Revision: 7411
Modified:
usrp2/trunk/fpga/eth/tx_prot_engine.v
Log:
implements updated protocol
Modified: usrp2/trunk/fpga/eth/tx_prot_engine.v
===================================================================
--- usrp2/trunk/fpga/eth/tx_prot_engine.v 2008-01-13 03:50:07 UTC (rev
7410)
+++ usrp2/trunk/fpga/eth/tx_prot_engine.v 2008-01-13 03:57:47 UTC (rev
7411)
@@ -52,10 +52,11 @@
.dataout(sfifo_out),.read(sfifo_read),.empty(empty));
// MAC side signals
+ // Inputs -- Tx_mac_wa, sfifo_out, empty
+ // outputs -- sfifo_read, Tx_mac_data, Tx_mac_wr, Tx_mac_BE, Tx_mac_sop,
Tx_mac_eop
+
// We are allowed to do one more write after we are told the FIFO is full
// This allows us to register the _wa signal and speed up timing.
-
- reg [7:0] tx_seqnum;
reg tx_mac_wa_d1;
always @(posedge clk)
tx_mac_wa_d1 <= Tx_mac_wa;
@@ -66,26 +67,26 @@
localparam PROT_HDR2 = 2;
localparam PROT_HDR3 = 3;
localparam PROT_HDR4 = 4;
- localparam PROT_PKT = 5;
- localparam PROT_TRAIL = 6;
+ localparam PROT_HDR5 = 5;
+ localparam PROT_PKT = 6;
+ reg [7:0] tx_seqnum;
always @(posedge clk)
if(rst)
tx_seqnum <= 0;
else if(set_stb & (set_addr == 36))
tx_seqnum <= set_data[7:0];
- else if(tx_mac_wa_d1 & (prot_state == PROT_TRAIL))
+ else if(tx_mac_wa_d1 & all_match & (prot_state == PROT_HDR5))
tx_seqnum <= tx_seqnum + 1;
always @(posedge clk)
if(rst)
prot_state <= PROT_IDLE;
else
- if(tx_mac_wa_d1)
+ if(tx_mac_wa_d1 & ~empty)
case(prot_state)
PROT_IDLE :
- if(~empty)
- prot_state <= PROT_HDR1;
+ prot_state <= PROT_HDR1;
PROT_HDR1 :
prot_state <= PROT_HDR2;
PROT_HDR2 :
@@ -93,29 +94,35 @@
PROT_HDR3 :
prot_state <= PROT_HDR4;
PROT_HDR4 :
+ prot_state <= PROT_HDR5;
+ PROT_HDR5 :
prot_state <= PROT_PKT;
PROT_PKT :
if(sfifo_out[32] & ~empty)
- prot_state <= PROT_TRAIL;
- PROT_TRAIL :
- prot_state <= PROT_IDLE; // seqnum increments here
+ prot_state <= PROT_IDLE;
default :
prot_state <= PROT_IDLE;
endcase // case(prot_state)
+ assign hdr_adr = {1'b0,prot_state};
+ wire match = (hdr_dat == sfifo_out[31:0]);
+ reg all_match;
+ always @(posedge clk)
+ if(prot_state == PROT_IDLE)
+ all_match <= 1;
+ else if(tx_mac_wa_d1 & ~empty &
+
((prot_state==PROT_HDR1)|(prot_state==PROT_HDR2)|(prot_state==PROT_HDR3)))
+ all_match <= all_match & match;
+
localparam ETH_TYPE = 16'hBEEF;
- assign Tx_mac_data = (prot_state == PROT_PKT) ? sfifo_out[31:0] :
- (prot_state == PROT_HDR4) ?
{ETH_TYPE,tx_channel,tx_seqnum} :
- (prot_state == PROT_TRAIL) ?
{rx_fifo_status,8'b0,rx_seqnum} :
- hdr_dat;
-
- assign hdr_adr = {1'b0,prot_state};
-
- assign sfifo_read = (prot_state == PROT_PKT) & ~empty & tx_mac_wa_d1;
- assign Tx_mac_wr = tx_mac_wa_d1 & (prot_state != PROT_IDLE) &
((prot_state != PROT_PKT)|~empty);
+ assign Tx_mac_data =
+ ((prot_state == PROT_HDR5) & all_match) ?
{rx_fifo_status,tx_seqnum,rx_seqnum} :
+ sfifo_out[31:0];
+ assign sfifo_read = (prot_state != PROT_IDLE) & ~empty & tx_mac_wa_d1;
+ assign Tx_mac_wr = sfifo_read;
assign Tx_mac_BE = 0; // Since we only deal with packets that are
multiples of 32 bits long
- assign Tx_mac_sop = (prot_state == PROT_HDR1); // sfifo_out[33];
- assign Tx_mac_eop = (prot_state == PROT_TRAIL); // sfifo_out[32];
+ assign Tx_mac_sop = sfifo_out[33];
+ assign Tx_mac_eop = sfifo_out[32];
// BUFFER side signals
reg xfer_active;
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